[PATCH v4 0/8] Add support for DMA2D of STMicroelectronics STM32 Soc series

From: Dillon Min <redacted>

This patchset introduces a basic support for DMA2D Interface
of STMicroelectronics STM32 SoC series.

This first basic support implements R2M, M2M, M2M_PFC
M2M_BLEND support will be added later on.

This has been tested on STM32469-DISCO board.

history
v4:
- replace V4L2_COLORFX_SET_ARGB, V4L2_CID_COLORFX_ARGB to
  V4L2_COLORFX_SET_RGB, V4L2_CID_COLORFX_RGB since Alpha paramter not used
  in current. thanks Hans.
v3 link:
https://lore.kernel.org/lkml/1633689012-14492-1-git-send-email-dillon.minfei@gmail.com/

v3:
- use V4L2_COLORFX_SET_ARGB, V4L2_CID_COLORFX_ARGB to pass argb paramter to
  the dma2d driver, instead of add stm32 private ioctl.
- some v2's patch are removed in this version.
  - "[PATCH v2 7/9] media: docs: add doc for the stm32 dma2d driver"
  - "[PATCH v2 8/9] media: v4l: uapi: Add user control base for stm32 dma2d
    controls"
- dma2d's driver changes based on Hans's review result. detail can be found at
  "media: stm32-dma2d: STM32 DMA2D driver"
- add stm32 clk drivers bugfix, ltdc clock disabled after kenerl boot up.
v3 based on kernel and v4l-utils git:

kernel:
commit 9e1ff307c779ce1f0f810c7ecce3d95bbae40896
Author: Linus Torvalds [off-list ref]
Date:   Sun Oct 3 14:08:47 2021 -0700

    Linux 5.15-rc4

v4l-utils:
commit 700f5ded9c6de2c6dfe5d1b453d85566f95b4f0c
Author: Hans Verkuil [off-list ref]
Date:   Sat Oct 2 11:01:05 2021 +0200

    test-media: show version info earlier and show cmd args

    Log the version info earlier and also log the command line arguments.
 
    Signed-off-by: Hans Verkuil [off-list ref]

v2 link:
https://lore.kernel.org/lkml/1626341068-20253-11-git-send-email-dillon.minfei@gmail.com/


v2:
- update v4l2-compliance to SHA: a4f2e3a6f306 2021-07-13 08:04:15
  the test results at below [1].
- introduce Documentation/userspace-api/media/drivers/stm32-uapi.rst
  to explain the detail of dma2d's ioctl.
- reserved 16 ioctls from v4l2-controls.h for stm32, introduce stm32-media.h.
- collect Reviewed-by tag from Rob Herring.
- update dma2d driver from Hans's review. the details can be found
  at related patches.
v1 link:
https://lore.kernel.org/lkml/1621508727-24486-1-git-send-email-dillon.minfei@gmail.com/

v1:
The commit based on kernel(master): c3d0e3fd41b7f0f5d5d5b6022ab7e813f04ea727

Note for v4l2-compliance tool on nu-mmu platform:
I add two change based on v4l-utils since commit:
f0c7e3d71eaf4182bae7eb3ee0e43b4eeb047ea9

- change fork() to vfork() in v4l2-test-controls.cpp
  since no-mmu platform don't include fork().

- bypass VIDIOC_QUERYCAP nullptr check
  I'm not sure if this is the bug from my cross compile tool
  which created by buildroot. user area's nullptr can't be
  detected by kernel side, i was try to add access_ok()
  in v4l2-ioctl.c, but no help

  If this case must be fixed, i will continue to debug it.
  the error log:
  ...
  fail: v4l2-compliance.cpp(623): doioctl(node, VIDIOC_QUERYCAP, nullptr) !=
  EFAULT
  ..

My changes on v4l2-compliance:

diff --git a/utils/v4l2-compliance/v4l2-compliance.cpp

b/utils/v4l2-compliance/v4l2-compliance.cpp
index 90a5036..a25fe4f 100644

--- a/utils/v4l2-compliance/v4l2-compliance.cpp
+++ b/utils/v4l2-compliance/v4l2-compliance.cpp

@@ -620,7 +620,7 @@ static int testCap(struct node *node)

        memset(&vcap, 0xff, sizeof(vcap));
        // Must always be there
-       fail_on_test(doioctl(node, VIDIOC_QUERYCAP, nullptr) != EFAULT);
+       //fail_on_test(doioctl(node, VIDIOC_QUERYCAP, nullptr) != EFAULT);
        fail_on_test(doioctl(node, VIDIOC_QUERYCAP, &vcap));
        fail_on_test(check_ustring(vcap.driver, sizeof(vcap.driver)));
        fail_on_test(check_ustring(vcap.card, sizeof(vcap.card)));

with v4l2-compliance test log (with above modification):
since the stm32f469-disco ram limitation, there are 25 failed on
dma_alloc_coherent()

Really appreciate if someone can help to test this patch on the STM32429I-EVAL
evaluation board (https://www.st.com/en/evaluation-tools/stm32429i-eval.html)
8M x 32-bit SDRAM, 1M x 16-bit SRAM and 8M x 16-bit NOR Flash

~ # free
              total        used        free      shared  buff/cache  available
Mem:          12760        4192        5248           0        3320       4740

~ # v4l2-compliance -f -d /dev/video0 > /dev/ttyprintk

[  170.952475] [U] v4l2-compliance 1.21.0-4855, 32 bits, 32-bit time_t
[  170.954056] [U] v4l2-compliance SHA: 700f5ded9c6d 2021-10-02 09:01:05
[  170.972848] [U] Compliance test for stm-dma2d device /dev/video0:
[  170.973783] [U] Driver Info:
[  170.974925] [U]      Driver name      : stm-dma2d
[  170.976127] [U]      Card type        : stm-dma2d
[  170.977381] [U]      Bus info         : platform:stm-dma2d
[  170.979806] [U]      Driver version   : 5.15.0
[  170.981027] [U]      Capabilities     : 0x84208000
[  170.982274] [U]              Video Memory-to-Memory
[  170.982963] [U]              Streaming
[  170.983707] [U]              Extended Pix Format
[  170.984490] [U]              Device Capabilities
[  170.985702] [U]      Device Caps      : 0x04208000
[  170.986919] [U]              Video Memory-to-Memory
[  170.987612] [U]              Streaming
[  170.989347] [U]              Extended Pix Format
[  170.990420] [U] Required ioctls:
[  170.991893] [U]      test VIDIOC_QUERYCAP: OK
[  171.018848] [U]      test invalid ioctls: OK
[  171.020047] [U] Allow for multiple opens:
[  171.024199] [U]      test second /dev/video0 open: OK
[  171.025734] [U]      test VIDIOC_QUERYCAP: OK
[  171.028089] [U]      test VIDIOC_G/S_PRIORITY: OK
[  171.251641] [U]      test for unlimited opens: OK
[  171.254558] [U] Debug ioctls:
[  171.256158] [U]      test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
[  171.257814] [U]      test VIDIOC_LOG_STATUS: OK (Not Supported)
[  171.261125] [U] Input ioctls:
[  171.262912] [U]      test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
[  171.264764] [U]      test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
[  171.266474] [U]      test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
[  171.268142] [U]      test VIDIOC_ENUMAUDIO: OK (Not Supported)
[  171.270551] [U]      test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
[  171.272100] [U]      test VIDIOC_G/S_AUDIO: OK (Not Supported)
[  171.273658] [U]      Inputs: 0 Audio Inputs: 0 Tuners: 0
[  171.274751] [U] Output ioctls:
[  171.276300] [U]      test VIDIOC_G/S_MODULATOR: OK (Not Supported)
[  171.278112] [U]      test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
[  171.280346] [U]      test VIDIOC_ENUMAUDOUT: OK (Not Supported)
[  171.282269] [U]      test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
[  171.283833] [U]      test VIDIOC_G/S_AUDOUT: OK (Not Supported)
[  171.285462] [U]      Outputs: 0 Audio Outputs: 0 Modulators: 0
[  171.286792] [U] Input/Output configuration ioctls:
[  171.288780] [U]      test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
[  171.290519] [U]      test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
[  171.292156] [U]      test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
[  171.293690] [U]      test VIDIOC_G/S_EDID: OK (Not Supported)
[  171.294971] [U] Control ioctls:
[  171.313809] [U]      test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
[  171.323488] [U]      test VIDIOC_QUERYCTRL: OK
[  171.330788] [U]      test VIDIOC_G/S_CTRL: OK
[  171.337979] [U]      test VIDIOC_G/S/TRY_EXT_CTRLS: OK
[  171.342892] [U]      test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
[  171.344750] [U]      test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
[  171.346272] [U]      Standard Controls: 3 Private Controls: 0
[  171.347509] [U] Format ioctls:
[  171.355495] [U]      test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
[  171.365472] [U]      test VIDIOC_G/S_PARM: OK (Not Supported)
[  171.367041] [U]      test VIDIOC_G_FBUF: OK (Not Supported)
[  171.371735] [U]      test VIDIOC_G_FMT: OK
[  171.373368] stm-dma2d 4002b000.dma2d: Format not supported: ffffffff, use the default.
[  172.351627] stm-dma2d 4002b000.dma2d: Format not supported: ffffffff, use the default.
[  173.330778] [U]      test VIDIOC_TRY_FMT: OK
[  173.331734] stm-dma2d 4002b000.dma2d: Format not supported: ffffffff, use the default.
[  174.312057] stm-dma2d 4002b000.dma2d: Format not supported: ffffffff, use the default.
[  175.294005] [U]      test VIDIOC_S_FMT: OK
[  175.297921] [U]      test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
[  175.308804] [U]      test Cropping: OK (Not Supported)
[  175.310695] [U]      test Composing: OK (Not Supported)
[  175.313135] [U]      test Scaling: OK
[  175.314308] [U] Codec ioctls:
[  175.315978] [U]      test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
[  175.317789] [U]      test VIDIOC_G_ENC_INDEX: OK (Not Supported)
[  175.325109] [U]      test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
[  175.327218] [U] Buffer ioctls:
[  175.451988] [U]      test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
[  175.503625] [U]      test VIDIOC_EXPBUF: OK
[  175.511170] [U]      test Requests: OK (Not Supported)
[  175.514256] [U]      test TIME32/64: OK
[  175.530160] [U] Test input 0:
[  175.532076] [U] Stream using all formats:
[  175.587253] [U]      Video Output: Frame #002 (select)
[  175.591403] [U]      Video Output: Frame #003 (select)
[  175.595150] [U]      Video Output: Frame #004 (select)
[  175.599310] [U]      Video Output: Frame #005 (select)
[  175.603053] [U]      Video Output: Frame #006 (select)
[  175.606784] [U]      Video Output: Frame #007 (select)
[  175.610924] [U]      Video Output: Frame #008 (select)
[  175.612864] [U]      Video Output: Frame #009 (select)
[  175.613996] [U]
[  175.615441] [U]      Video Capture: Captured 8 buffers
[  175.621462] [U]      BA24 (32-bit ARGB 8-8-8-8) 1x1 -> BA24 (32-bit ARGB 8-8-8-8) 1x1: OK
[  175.658951] [U]      Video Output: Frame #002 (select)
[  175.662691] [U]      Video Output: Frame #003 (select)
[  175.666439] [U]      Video Output: Frame #004 (select)
[  175.670586] [U]      Video Output: Frame #005 (select)
[  175.674325] [U]      Video Output: Frame #006 (select)
[  175.678063] [U]      Video Output: Frame #007 (select)
[  175.682201] [U]      Video Output: Frame #008 (select)
[  175.684142] [U]      Video Output: Frame #009 (select)
[  175.685274] [U]
[  175.686713] [U]      Video Capture: Captured 8 buffers
[  175.691870] [U]      BA24 (32-bit ARGB 8-8-8-8) 1x1 -> RGB3 (24-bit RGB 8-8-8) 1x1: OK
[  175.730355] [U]      Video Output: Frame #002 (select)
[  175.734094] [U]      Video Output: Frame #003 (select)
[  175.737829] [U]      Video Output: Frame #004 (select)
[  175.741979] [U]      Video Output: Frame #005 (select)
[  175.745715] [U]      Video Output: Frame #006 (select)
[  175.749884] [U]      Video Output: Frame #007 (select)
[  175.753573] [U]      Video Output: Frame #008 (select)
[  175.755491] [U]      Video Output: Frame #009 (select)
[  175.756622] [U]
[  175.758071] [U]      Video Capture: Captured 8 buffers
[  175.763227] [U]      BA24 (32-bit ARGB 8-8-8-8) 1x1 -> RGBP (16-bit RGB 5-6-5) 1x1: OK
[  175.800838] [U]      Video Output: Frame #002 (select)
[  175.804545] [U]      Video Output: Frame #003 (select)
[  175.808701] [U]      Video Output: Frame #004 (select)
[  175.812444] [U]      Video Output: Frame #005 (select)
[  175.816183] [U]      Video Output: Frame #006 (select)
[  175.820334] [U]      Video Output: Frame #007 (select)
[  175.824073] [U]      Video Output: Frame #008 (select)
[  175.826009] [U]      Video Output: Frame #009 (select)
[  175.827115] [U]
[  175.828971] [U]      Video Capture: Captured 8 buffers
[  175.833740] [U]      BA24 (32-bit ARGB 8-8-8-8) 1x1 -> AR15 (16-bit ARGB 1-5-5-5) 1x1: OK
[  175.871292] [U]      Video Output: Frame #002 (select)
[  175.875000] [U]      Video Output: Frame #003 (select)
[  175.879136] [U]      Video Output: Frame #004 (select)
[  175.882879] [U]      Video Output: Frame #005 (select)
[  175.886616] [U]      Video Output: Frame #006 (select)
[  175.890776] [U]      Video Output: Frame #007 (select)
[  175.894514] [U]      Video Output: Frame #008 (select)
[  175.896453] [U]      Video Output: Frame #009 (select)
[  175.897589] [U]
[  175.899445] [U]      Video Capture: Captured 8 buffers
[  175.904203] [U]      BA24 (32-bit ARGB 8-8-8-8) 1x1 -> AR12 (16-bit ARGB 4-4-4-4) 1x1: OK
[  175.909257] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -323584 failed
[  176.887971] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  176.891254] [U]      BA24 (32-bit ARGB 8-8-8-8) 16383x65535 -> BA24 (32-bit ARGB 8-8-8-8) 16383x65535: FAIL
[  176.894591] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -323584 failed
[  177.872809] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  177.875613] [U]      BA24 (32-bit ARGB 8-8-8-8) 16383x65535 -> RGB3 (24-bit RGB 8-8-8) 16383x65535: FAIL
[  177.879358] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -323584 failed
[  178.859498] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  178.863900] [U]      BA24 (32-bit ARGB 8-8-8-8) 16383x65535 -> RGBP (16-bit RGB 5-6-5) 16383x65535: FAIL
[  178.877499] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -323584 failed
[  179.861912] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  179.865414] [U]      BA24 (32-bit ARGB 8-8-8-8) 16383x65535 -> AR15 (16-bit ARGB 1-5-5-5) 16383x65535: FAIL
[  179.869176] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -323584 failed
[  180.847874] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  180.851154] [U]      BA24 (32-bit ARGB 8-8-8-8) 16383x65535 -> AR12 (16-bit ARGB 4-4-4-4) 16383x65535: FAIL
[  181.012396] [U]      Video Output: Frame #002 (select)
[  181.023820] [U]      Video Output: Frame #003 (select)
[  181.027866] [U]      Video Output: Frame #004 (select)
[  181.033480] [U]      Video Output: Frame #005 (select)
[  181.039683] [U]      Video Output: Frame #006 (select)
[  181.044731] [U]      Video Output: Frame #007 (select)
[  181.054462] [U]      Video Output: Frame #008 (select)
[  181.057047] [U]      Video Output: Frame #009 (select)
[  181.060148] [U]
[  181.062534] [U]      Video Capture: Captured 8 buffers
[  181.079381] [U]      BA24 (32-bit ARGB 8-8-8-8) 240x320 -> BA24 (32-bit ARGB 8-8-8-8) 240x320: OK
[  181.211005] [U]      Video Output: Frame #002 (select)
[  181.216086] [U]      Video Output: Frame #003 (select)
[  181.221810] [U]      Video Output: Frame #004 (select)
[  181.227030] [U]      Video Output: Frame #005 (select)
[  181.232749] [U]      Video Output: Frame #006 (select)
[  181.237824] [U]      Video Output: Frame #007 (select)
[  181.243524] [U]      Video Output: Frame #008 (select)
[  181.246555] [U]      Video Output: Frame #009 (select)
[  181.247687] [U]
[  181.249550] [U]      Video Capture: Captured 8 buffers
[  181.257051] [U]      BA24 (32-bit ARGB 8-8-8-8) 240x320 -> RGB3 (24-bit RGB 8-8-8) 240x320: OK
[  181.379887] [U]      Video Output: Frame #002 (select)
[  181.384861] [U]      Video Output: Frame #003 (select)
[  181.390275] [U]      Video Output: Frame #004 (select)
[  181.395316] [U]      Video Output: Frame #005 (select)
[  181.400843] [U]      Video Output: Frame #006 (select)
[  181.405823] [U]      Video Output: Frame #007 (select)
[  181.411116] [U]      Video Output: Frame #008 (select)
[  181.414056] [U]      Video Output: Frame #009 (select)
[  181.415187] [U]
[  181.416633] [U]      Video Capture: Captured 8 buffers
[  181.424542] [U]      BA24 (32-bit ARGB 8-8-8-8) 240x320 -> RGBP (16-bit RGB 5-6-5) 240x320: OK
[  181.546524] [U]      Video Output: Frame #002 (select)
[  181.551867] [U]      Video Output: Frame #003 (select)
[  181.556967] [U]      Video Output: Frame #004 (select)
[  181.562273] [U]      Video Output: Frame #005 (select)
[  181.567476] [U]      Video Output: Frame #006 (select)
[  181.572775] [U]      Video Output: Frame #007 (select)
[  181.577885] [U]      Video Output: Frame #008 (select)
[  181.581013] [U]      Video Output: Frame #009 (select)
[  181.582141] [U]
[  181.583584] [U]      Video Capture: Captured 8 buffers
[  181.591533] [U]      BA24 (32-bit ARGB 8-8-8-8) 240x320 -> AR15 (16-bit ARGB 1-5-5-5) 240x320: OK
[  181.713820] [U]      Video Output: Frame #002 (select)
[  181.719521] [U]      Video Output: Frame #003 (select)
[  181.724220] [U]      Video Output: Frame #004 (select)
[  181.729876] [U]      Video Output: Frame #005 (select)
[  181.734685] [U]      Video Output: Frame #006 (select)
[  181.740368] [U]      Video Output: Frame #007 (select)
[  181.745185] [U]      Video Output: Frame #008 (select)
[  181.748087] [U]      Video Output: Frame #009 (select)
[  181.749610] [U]
[  181.751056] [U]      Video Capture: Captured 8 buffers
[  181.759012] [U]      BA24 (32-bit ARGB 8-8-8-8) 240x320 -> AR12 (16-bit ARGB 4-4-4-4) 240x320: OK
[  181.798926] [U]      Video Output: Frame #002 (select)
[  181.802765] [U]      Video Output: Frame #003 (select)
[  181.806506] [U]      Video Output: Frame #004 (select)
[  181.810661] [U]      Video Output: Frame #005 (select)
[  181.814404] [U]      Video Output: Frame #006 (select)
[  181.818563] [U]      Video Output: Frame #007 (select)
[  181.822249] [U]      Video Output: Frame #008 (select)
[  181.824192] [U]      Video Output: Frame #009 (select)
[  181.825320] [U]
[  181.826762] [U]      Video Capture: Captured 8 buffers
[  181.831920] [U]      RGB3 (24-bit RGB 8-8-8) 1x1 -> BA24 (32-bit ARGB 8-8-8-8) 1x1: OK
[  181.869600] [U]      Video Output: Frame #002 (select)
[  181.873312] [U]      Video Output: Frame #003 (select)
[  181.877055] [U]      Video Output: Frame #004 (select)
[  181.881214] [U]      Video Output: Frame #005 (select)
[  181.884958] [U]      Video Output: Frame #006 (select)
[  181.890046] [U]      Video Output: Frame #007 (select)
[  181.893793] [U]      Video Output: Frame #008 (select)
[  181.895699] [U]      Video Output: Frame #009 (select)
[  181.896828] [U]
[  181.898693] [U]      Video Capture: Captured 8 buffers
[  181.903395] [U]      RGB3 (24-bit RGB 8-8-8) 1x1 -> RGB3 (24-bit RGB 8-8-8) 1x1: OK
[  181.940908] [U]      Video Output: Frame #002 (select)
[  181.944624] [U]      Video Output: Frame #003 (select)
[  181.948778] [U]      Video Output: Frame #004 (select)
[  181.952520] [U]      Video Output: Frame #005 (select)
[  181.956269] [U]      Video Output: Frame #006 (select)
[  181.960434] [U]      Video Output: Frame #007 (select)
[  181.964171] [U]      Video Output: Frame #008 (select)
[  181.966115] [U]      Video Output: Frame #009 (select)
[  181.967247] [U]
[  181.969039] [U]      Video Capture: Captured 8 buffers
[  181.973749] [U]      RGB3 (24-bit RGB 8-8-8) 1x1 -> RGBP (16-bit RGB 5-6-5) 1x1: OK
[  182.011230] [U]      Video Output: Frame #002 (select)
[  182.014969] [U]      Video Output: Frame #003 (select)
[  182.019098] [U]      Video Output: Frame #004 (select)
[  182.022842] [U]      Video Output: Frame #005 (select)
[  182.026583] [U]      Video Output: Frame #006 (select)
[  182.030919] [U]      Video Output: Frame #007 (select)
[  182.034663] [U]      Video Output: Frame #008 (select)
[  182.036602] [U]      Video Output: Frame #009 (select)
[  182.037730] [U]
[  182.039583] [U]      Video Capture: Captured 8 buffers
[  182.044294] [U]      RGB3 (24-bit RGB 8-8-8) 1x1 -> AR15 (16-bit ARGB 1-5-5-5) 1x1: OK
[  182.081844] [U]      Video Output: Frame #002 (select)
[  182.085683] [U]      Video Output: Frame #003 (select)
[  182.089794] [U]      Video Output: Frame #004 (select)
[  182.093529] [U]      Video Output: Frame #005 (select)
[  182.097275] [U]      Video Output: Frame #006 (select)
[  182.102306] [U]      Video Output: Frame #007 (select)
[  182.106058] [U]      Video Output: Frame #008 (select)
[  182.107993] [U]      Video Output: Frame #009 (select)
[  182.109717] [U]
[  182.111164] [U]      Video Capture: Captured 8 buffers
[  182.115800] [U]      RGB3 (24-bit RGB 8-8-8) 1x1 -> AR12 (16-bit ARGB 4-4-4-4) 1x1: OK
[  182.120866] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -1073983488 failed
[  183.101917] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  183.104837] [U]      RGB3 (24-bit RGB 8-8-8) 16383x65535 -> BA24 (32-bit ARGB 8-8-8-8) 16383x65535: FAIL
[  183.108595] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -1073983488 failed
[  184.088869] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  184.091774] [U]      RGB3 (24-bit RGB 8-8-8) 16383x65535 -> RGB3 (24-bit RGB 8-8-8) 16383x65535: FAIL
[  184.095134] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -1073983488 failed
[  185.076687] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  185.081734] [U]      RGB3 (24-bit RGB 8-8-8) 16383x65535 -> RGBP (16-bit RGB 5-6-5) 16383x65535: FAIL
[  185.089520] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -1073983488 failed
[  186.075117] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  186.078050] [U]      RGB3 (24-bit RGB 8-8-8) 16383x65535 -> AR15 (16-bit ARGB 1-5-5-5) 16383x65535: FAIL
[  186.087047] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size -1073983488 failed
[  187.067454] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  187.070722] [U]      RGB3 (24-bit RGB 8-8-8) 16383x65535 -> AR12 (16-bit ARGB 4-4-4-4) 16383x65535: FAIL
[  187.208952] [U]      Video Output: Frame #002 (select)
[  187.213072] [U]      Video Output: Frame #003 (select)
[  187.217909] [U]      Video Output: Frame #004 (select)
[  187.230839] [U]      Video Output: Frame #005 (select)
[  187.236159] [U]      Video Output: Frame #006 (select)
[  187.241721] [U]      Video Output: Frame #007 (select)
[  187.247706] [U]      Video Output: Frame #008 (select)
[  187.250878] [U]      Video Output: Frame #009 (select)
[  187.252028] [U]
[  187.253484] [U]      Video Capture: Captured 8 buffers
[  187.263075] [U]      RGB3 (24-bit RGB 8-8-8) 240x320 -> BA24 (32-bit ARGB 8-8-8-8) 240x320: OK
[  187.384437] [U]      Video Output: Frame #002 (select)
[  187.390173] [U]      Video Output: Frame #003 (select)
[  187.395043] [U]      Video Output: Frame #004 (select)
[  187.400563] [U]      Video Output: Frame #005 (select)
[  187.405436] [U]      Video Output: Frame #006 (select)
[  187.410860] [U]      Video Output: Frame #007 (select)
[  187.415903] [U]      Video Output: Frame #008 (select)
[  187.419300] [U]      Video Output: Frame #009 (select)
[  187.420445] [U]
[  187.421882] [U]      Video Capture: Captured 8 buffers
[  187.428304] [U]      RGB3 (24-bit RGB 8-8-8) 240x320 -> RGB3 (24-bit RGB 8-8-8) 240x320: OK
[  187.527404] [U]      Video Output: Frame #002 (select)
[  187.532721] [U]      Video Output: Frame #003 (select)
[  187.537565] [U]      Video Output: Frame #004 (select)
[  187.542892] [U]      Video Output: Frame #005 (select)
[  187.547735] [U]      Video Output: Frame #006 (select)
[  187.552979] [U]      Video Output: Frame #007 (select)
[  187.557815] [U]      Video Output: Frame #008 (select)
[  187.560977] [U]      Video Output: Frame #009 (select)
[  187.562108] [U]
[  187.563568] [U]      Video Capture: Captured 8 buffers
[  187.570508] [U]      RGB3 (24-bit RGB 8-8-8) 240x320 -> RGBP (16-bit RGB 5-6-5) 240x320: OK
[  187.669153] [U]      Video Output: Frame #002 (select)
[  187.673836] [U]      Video Output: Frame #003 (select)
[  187.679199] [U]      Video Output: Frame #004 (select)
[  187.683921] [U]      Video Output: Frame #005 (select)
[  187.690806] [U]      Video Output: Frame #006 (select)
[  187.694700] [U]      Video Output: Frame #007 (select)
[  187.700031] [U]      Video Output: Frame #008 (select)
[  187.702729] [U]      Video Output: Frame #009 (select)
[  187.703862] [U]
[  187.705315] [U]      Video Capture: Captured 8 buffers
[  187.712301] [U]      RGB3 (24-bit RGB 8-8-8) 240x320 -> AR15 (16-bit ARGB 1-5-5-5) 240x320: OK
[  187.810853] [U]      Video Output: Frame #002 (select)
[  187.815718] [U]      Video Output: Frame #003 (select)
[  187.820886] [U]      Video Output: Frame #004 (select)
[  187.825738] [U]      Video Output: Frame #005 (select)
[  187.830998] [U]      Video Output: Frame #006 (select)
[  187.835854] [U]      Video Output: Frame #007 (select)
[  187.840962] [U]      Video Output: Frame #008 (select)
[  187.843658] [U]      Video Output: Frame #009 (select)
[  187.844808] [U]
[  187.846267] [U]      Video Capture: Captured 8 buffers
[  187.853233] [U]      RGB3 (24-bit RGB 8-8-8) 240x320 -> AR12 (16-bit ARGB 4-4-4-4) 240x320: OK
[  187.892982] [U]      Video Output: Frame #002 (select)
[  187.896722] [U]      Video Output: Frame #003 (select)
[  187.901814] [U]      Video Output: Frame #004 (select)
[  187.905570] [U]      Video Output: Frame #005 (select)
[  187.909747] [U]      Video Output: Frame #006 (select)
[  187.913502] [U]      Video Output: Frame #007 (select)
[  187.917221] [U]      Video Output: Frame #008 (select)
[  187.919598] [U]      Video Output: Frame #009 (select)
[  187.920744] [U]
[  187.922187] [U]      Video Capture: Captured 8 buffers
[  187.926949] [U]      RGBP (16-bit RGB 5-6-5) 1x1 -> BA24 (32-bit ARGB 8-8-8-8) 1x1: OK
[  187.964548] [U]      Video Output: Frame #002 (select)
[  187.968710] [U]      Video Output: Frame #003 (select)
[  187.972450] [U]      Video Output: Frame #004 (select)
[  187.976200] [U]      Video Output: Frame #005 (select)
[  187.980386] [U]      Video Output: Frame #006 (select)
[  187.984129] [U]      Video Output: Frame #007 (select)
[  187.987832] [U]      Video Output: Frame #008 (select)
[  187.990200] [U]      Video Output: Frame #009 (select)
[  187.991334] [U]
[  187.992794] [U]      Video Capture: Captured 8 buffers
[  187.997518] [U]      RGBP (16-bit RGB 5-6-5) 1x1 -> RGB3 (24-bit RGB 8-8-8) 1x1: OK
[  188.035225] [U]      Video Output: Frame #002 (select)
[  188.039367] [U]      Video Output: Frame #003 (select)
[  188.043100] [U]      Video Output: Frame #004 (select)
[  188.046869] [U]      Video Output: Frame #005 (select)
[  188.051043] [U]      Video Output: Frame #006 (select)
[  188.054779] [U]      Video Output: Frame #007 (select)
[  188.058952] [U]      Video Output: Frame #008 (select)
[  188.060869] [U]      Video Output: Frame #009 (select)
[  188.062007] [U]
[  188.063481] [U]      Video Capture: Captured 8 buffers
[  188.068199] [U]      RGBP (16-bit RGB 5-6-5) 1x1 -> RGBP (16-bit RGB 5-6-5) 1x1: OK
[  188.105750] [U]      Video Output: Frame #002 (select)
[  188.110628] [U]      Video Output: Frame #003 (select)
[  188.114400] [U]      Video Output: Frame #004 (select)
[  188.118583] [U]      Video Output: Frame #005 (select)
[  188.122346] [U]      Video Output: Frame #006 (select)
[  188.126112] [U]      Video Output: Frame #007 (select)
[  188.130297] [U]      Video Output: Frame #008 (select)
[  188.132256] [U]      Video Output: Frame #009 (select)
[  188.133395] [U]
[  188.134832] [U]      Video Capture: Captured 8 buffers
[  188.139980] [U]      RGBP (16-bit RGB 5-6-5) 1x1 -> AR15 (16-bit ARGB 1-5-5-5) 1x1: OK
[  188.177179] [U]      Video Output: Frame #002 (select)
[  188.181359] [U]      Video Output: Frame #003 (select)
[  188.185092] [U]      Video Output: Frame #004 (select)
[  188.189256] [U]      Video Output: Frame #005 (select)
[  188.193014] [U]      Video Output: Frame #006 (select)
[  188.196782] [U]      Video Output: Frame #007 (select)
[  188.200966] [U]      Video Output: Frame #008 (select)
[  188.202927] [U]      Video Output: Frame #009 (select)
[  188.204076] [U]
[  188.205539] [U]      Video Capture: Captured 8 buffers
[  188.210672] [U]      RGBP (16-bit RGB 5-6-5) 1x1 -> AR12 (16-bit ARGB 4-4-4-4) 1x1: OK
[  188.215307] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  189.195288] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  189.198221] [U]      RGBP (16-bit RGB 5-6-5) 16383x65535 -> BA24 (32-bit ARGB 8-8-8-8) 16383x65535: FAIL
[  189.201999] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  190.181652] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  190.184584] [U]      RGBP (16-bit RGB 5-6-5) 16383x65535 -> RGB3 (24-bit RGB 8-8-8) 16383x65535: FAIL
[  190.187942] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  191.169734] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  191.174128] [U]      RGBP (16-bit RGB 5-6-5) 16383x65535 -> RGBP (16-bit RGB 5-6-5) 16383x65535: FAIL
[  191.187757] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  192.173031] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  192.176513] [U]      RGBP (16-bit RGB 5-6-5) 16383x65535 -> AR15 (16-bit ARGB 1-5-5-5) 16383x65535: FAIL
[  192.180243] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  193.160460] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  193.163402] [U]      RGBP (16-bit RGB 5-6-5) 16383x65535 -> AR12 (16-bit ARGB 4-4-4-4) 16383x65535: FAIL
[  193.274947] [U]      Video Output: Frame #002 (select)
[  193.280280] [U]      Video Output: Frame #003 (select)
[  193.285134] [U]      Video Output: Frame #004 (select)
[  193.293553] [U]      Video Output: Frame #005 (select)
[  193.301976] [U]      Video Output: Frame #006 (select)
[  193.313308] [U]      Video Output: Frame #007 (select)
[  193.321840] [U]      Video Output: Frame #008 (select)
[  193.324248] [U]      Video Output: Frame #009 (select)
[  193.325401] [U]
[  193.326861] [U]      Video Capture: Captured 8 buffers
[  193.337747] [U]      RGBP (16-bit RGB 5-6-5) 240x320 -> BA24 (32-bit ARGB 8-8-8-8) 240x320: OK
[  193.444950] [U]      Video Output: Frame #002 (select)
[  193.450224] [U]      Video Output: Frame #003 (select)
[  193.455052] [U]      Video Output: Frame #004 (select)
[  193.460319] [U]      Video Output: Frame #005 (select)
[  193.465127] [U]      Video Output: Frame #006 (select)
[  193.470305] [U]      Video Output: Frame #007 (select)
[  193.475099] [U]      Video Output: Frame #008 (select)
[  193.477842] [U]      Video Output: Frame #009 (select)
[  193.479391] [U]
[  193.480851] [U]      Video Capture: Captured 8 buffers
[  193.487404] [U]      RGBP (16-bit RGB 5-6-5) 240x320 -> RGB3 (24-bit RGB 8-8-8) 240x320: OK
[  193.571393] [U]      Video Output: Frame #002 (select)
[  193.576229] [U]      Video Output: Frame #003 (select)
[  193.581437] [U]      Video Output: Frame #004 (select)
[  193.586293] [U]      Video Output: Frame #005 (select)
[  193.591485] [U]      Video Output: Frame #006 (select)
[  193.596283] [U]      Video Output: Frame #007 (select)
[  193.601494] [U]      Video Output: Frame #008 (select)
[  193.604143] [U]      Video Output: Frame #009 (select)
[  193.605292] [U]
[  193.606751] [U]      Video Capture: Captured 8 buffers
[  193.613713] [U]      RGBP (16-bit RGB 5-6-5) 240x320 -> RGBP (16-bit RGB 5-6-5) 240x320: OK
[  193.697074] [U]      Video Output: Frame #002 (select)
[  193.702220] [U]      Video Output: Frame #003 (select)
[  193.707044] [U]      Video Output: Frame #004 (select)
[  193.712181] [U]      Video Output: Frame #005 (select)
[  193.716969] [U]      Video Output: Frame #006 (select)
[  193.722108] [U]      Video Output: Frame #007 (select)
[  193.726946] [U]      Video Output: Frame #008 (select)
[  193.730038] [U]      Video Output: Frame #009 (select)
[  193.731174] [U]
[  193.732631] [U]      Video Capture: Captured 8 buffers
[  193.739533] [U]      RGBP (16-bit RGB 5-6-5) 240x320 -> AR15 (16-bit ARGB 1-5-5-5) 240x320: OK
[  193.822311] [U]      Video Output: Frame #002 (select)
[  193.827146] [U]      Video Output: Frame #003 (select)
[  193.832330] [U]      Video Output: Frame #004 (select)
[  193.837059] [U]      Video Output: Frame #005 (select)
[  193.842231] [U]      Video Output: Frame #006 (select)
[  193.847059] [U]      Video Output: Frame #007 (select)
[  193.852850] [U]      Video Output: Frame #008 (select)
[  193.855495] [U]      Video Output: Frame #009 (select)
[  193.856643] [U]
[  193.858101] [U]      Video Capture: Captured 8 buffers
[  193.865073] [U]      RGBP (16-bit RGB 5-6-5) 240x320 -> AR12 (16-bit ARGB 4-4-4-4) 240x320: OK
[  193.904824] [U]      Video Output: Frame #002 (select)
[  193.909125] [U]      Video Output: Frame #003 (select)
[  193.912856] [U]      Video Output: Frame #004 (select)
[  193.916610] [U]      Video Output: Frame #005 (select)
[  193.920775] [U]      Video Output: Frame #006 (select)
[  193.924532] [U]      Video Output: Frame #007 (select)
[  193.928706] [U]      Video Output: Frame #008 (select)
[  193.930651] [U]      Video Output: Frame #009 (select)
[  193.931794] [U]
[  193.933234] [U]      Video Capture: Captured 8 buffers
[  193.938007] [U]      AR15 (16-bit ARGB 1-5-5-5) 1x1 -> BA24 (32-bit ARGB 8-8-8-8) 1x1: OK
[  193.975577] [U]      Video Output: Frame #002 (select)
[  193.979749] [U]      Video Output: Frame #003 (select)
[  193.983475] [U]      Video Output: Frame #004 (select)
[  193.987350] [U]      Video Output: Frame #005 (select)
[  193.991683] [U]      Video Output: Frame #006 (select)
[  193.995434] [U]      Video Output: Frame #007 (select)
[  193.999608] [U]      Video Output: Frame #008 (select)
[  194.001553] [U]      Video Output: Frame #009 (select)
[  194.002712] [U]
[  194.004171] [U]      Video Capture: Captured 8 buffers
[  194.009333] [U]      AR15 (16-bit ARGB 1-5-5-5) 1x1 -> RGB3 (24-bit RGB 8-8-8) 1x1: OK
[  194.046472] [U]      Video Output: Frame #002 (select)
[  194.050656] [U]      Video Output: Frame #003 (select)
[  194.054421] [U]      Video Output: Frame #004 (select)
[  194.059442] [U]      Video Output: Frame #005 (select)
[  194.063218] [U]      Video Output: Frame #006 (select)
[  194.066975] [U]      Video Output: Frame #007 (select)
[  194.071160] [U]      Video Output: Frame #008 (select)
[  194.073114] [U]      Video Output: Frame #009 (select)
[  194.074265] [U]
[  194.075723] [U]      Video Capture: Captured 8 buffers
[  194.080748] [U]      AR15 (16-bit ARGB 1-5-5-5) 1x1 -> RGBP (16-bit RGB 5-6-5) 1x1: OK
[  194.117903] [U]      Video Output: Frame #002 (select)
[  194.122071] [U]      Video Output: Frame #003 (select)
[  194.125830] [U]      Video Output: Frame #004 (select)
[  194.130014] [U]      Video Output: Frame #005 (select)
[  194.133781] [U]      Video Output: Frame #006 (select)
[  194.137536] [U]      Video Output: Frame #007 (select)
[  194.141720] [U]      Video Output: Frame #008 (select)
[  194.143679] [U]      Video Output: Frame #009 (select)
[  194.144831] [U]
[  194.146297] [U]      Video Capture: Captured 8 buffers
[  194.151510] [U]      AR15 (16-bit ARGB 1-5-5-5) 1x1 -> AR15 (16-bit ARGB 1-5-5-5) 1x1: OK
[  194.189253] [U]      Video Output: Frame #002 (select)
[  194.192994] [U]      Video Output: Frame #003 (select)
[  194.196765] [U]      Video Output: Frame #004 (select)
[  194.200932] [U]      Video Output: Frame #005 (select)
[  194.204676] [U]      Video Output: Frame #006 (select)
[  194.208846] [U]      Video Output: Frame #007 (select)
[  194.212618] [U]      Video Output: Frame #008 (select)
[  194.214580] [U]      Video Output: Frame #009 (select)
[  194.215730] [U]
[  194.217192] [U]      Video Capture: Captured 8 buffers
[  194.222410] [U]      AR15 (16-bit ARGB 1-5-5-5) 1x1 -> AR12 (16-bit ARGB 4-4-4-4) 1x1: OK
[  194.226996] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  195.208033] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  195.211335] [U]      AR15 (16-bit ARGB 1-5-5-5) 16383x65535 -> BA24 (32-bit ARGB 8-8-8-8) 16383x65535: FAIL
[  195.214694] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  196.195051] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  196.198000] [U]      AR15 (16-bit ARGB 1-5-5-5) 16383x65535 -> RGB3 (24-bit RGB 8-8-8) 16383x65535: FAIL
[  196.201760] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  197.187625] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  197.192418] [U]      AR15 (16-bit ARGB 1-5-5-5) 16383x65535 -> RGBP (16-bit RGB 5-6-5) 16383x65535: FAIL
[  197.205998] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  198.201823] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  198.205331] [U]      AR15 (16-bit ARGB 1-5-5-5) 16383x65535 -> AR15 (16-bit ARGB 1-5-5-5) 16383x65535: FAIL
[  198.209147] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  199.200108] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  199.203095] [U]      AR15 (16-bit ARGB 1-5-5-5) 16383x65535 -> AR12 (16-bit ARGB 4-4-4-4) 16383x65535: FAIL
[  199.320434] [U]      Video Output: Frame #002 (select)
[  199.331236] [U]      Video Output: Frame #003 (select)
[  199.341665] [U]      Video Output: Frame #004 (select)
[  199.347031] [U]      Video Output: Frame #005 (select)
[  199.352378] [U]      Video Output: Frame #006 (select)
[  199.358615] [U]      Video Output: Frame #007 (select)
[  199.363360] [U]      Video Output: Frame #008 (select)
[  199.366138] [U]      Video Output: Frame #009 (select)
[  199.367286] [U]
[  199.369727] [U]      Video Capture: Captured 8 buffers
[  199.382735] [U]      AR15 (16-bit ARGB 1-5-5-5) 240x320 -> BA24 (32-bit ARGB 8-8-8-8) 240x320: OK
[  199.483770] [U]      Video Output: Frame #002 (select)
[  199.489043] [U]      Video Output: Frame #003 (select)
[  199.493805] [U]      Video Output: Frame #004 (select)
[  199.499082] [U]      Video Output: Frame #005 (select)
[  199.503887] [U]      Video Output: Frame #006 (select)
[  199.509167] [U]      Video Output: Frame #007 (select)
[  199.513904] [U]      Video Output: Frame #008 (select)
[  199.516589] [U]      Video Output: Frame #009 (select)
[  199.517738] [U]
[  199.519612] [U]      Video Capture: Captured 8 buffers
[  199.526169] [U]      AR15 (16-bit ARGB 1-5-5-5) 240x320 -> RGB3 (24-bit RGB 8-8-8) 240x320: OK
[  199.610204] [U]      Video Output: Frame #002 (select)
[  199.614310] [U]      Video Output: Frame #003 (select)
[  199.619549] [U]      Video Output: Frame #004 (select)
[  199.624324] [U]      Video Output: Frame #005 (select)
[  199.629555] [U]      Video Output: Frame #006 (select)
[  199.634317] [U]      Video Output: Frame #007 (select)
[  199.639537] [U]      Video Output: Frame #008 (select)
[  199.642094] [U]      Video Output: Frame #009 (select)
[  199.643240] [U]
[  199.644701] [U]      Video Capture: Captured 8 buffers
[  199.651701] [U]      AR15 (16-bit ARGB 1-5-5-5) 240x320 -> RGBP (16-bit RGB 5-6-5) 240x320: OK
[  199.734579] [U]      Video Output: Frame #002 (select)
[  199.739783] [U]      Video Output: Frame #003 (select)
[  199.744573] [U]      Video Output: Frame #004 (select)
[  199.749801] [U]      Video Output: Frame #005 (select)
[  199.754565] [U]      Video Output: Frame #006 (select)
[  199.760306] [U]      Video Output: Frame #007 (select)
[  199.764463] [U]      Video Output: Frame #008 (select)
[  199.767129] [U]      Video Output: Frame #009 (select)
[  199.768671] [U]
[  199.770128] [U]      Video Capture: Captured 8 buffers
[  199.776725] [U]      AR15 (16-bit ARGB 1-5-5-5) 240x320 -> AR15 (16-bit ARGB 1-5-5-5) 240x320: OK
[  199.860726] [U]      Video Output: Frame #002 (select)
[  199.865549] [U]      Video Output: Frame #003 (select)
[  199.870735] [U]      Video Output: Frame #004 (select)
[  199.875558] [U]      Video Output: Frame #005 (select)
[  199.880566] [U]      Video Output: Frame #006 (select)
[  199.885390] [U]      Video Output: Frame #007 (select)
[  199.890633] [U]      Video Output: Frame #008 (select)
[  199.893191] [U]      Video Output: Frame #009 (select)
[  199.894336] [U]
[  199.895803] [U]      Video Capture: Captured 8 buffers
[  199.902832] [U]      AR15 (16-bit ARGB 1-5-5-5) 240x320 -> AR12 (16-bit ARGB 4-4-4-4) 240x320: OK
[  199.942759] [U]      Video Output: Frame #002 (select)
[  199.946516] [U]      Video Output: Frame #003 (select)
[  199.950683] [U]      Video Output: Frame #004 (select)
[  199.954398] [U]      Video Output: Frame #005 (select)
[  199.958570] [U]      Video Output: Frame #006 (select)
[  199.962304] [U]      Video Output: Frame #007 (select)
[  199.966066] [U]      Video Output: Frame #008 (select)
[  199.968022] [U]      Video Output: Frame #009 (select)
[  199.969581] [U]
[  199.971038] [U]      Video Capture: Captured 8 buffers
[  199.975816] [U]      AR12 (16-bit ARGB 4-4-4-4) 1x1 -> BA24 (32-bit ARGB 8-8-8-8) 1x1: OK
[  200.013529] [U]      Video Output: Frame #002 (select)
[  200.017282] [U]      Video Output: Frame #003 (select)
[  200.021558] [U]      Video Output: Frame #004 (select)
[  200.025307] [U]      Video Output: Frame #005 (select)
[  200.030378] [U]      Video Output: Frame #006 (select)
[  200.034117] [U]      Video Output: Frame #007 (select)
[  200.037879] [U]      Video Output: Frame #008 (select)
[  200.040251] [U]      Video Output: Frame #009 (select)
[  200.041403] [U]
[  200.042867] [U]      Video Capture: Captured 8 buffers
[  200.047628] [U]      AR12 (16-bit ARGB 4-4-4-4) 1x1 -> RGB3 (24-bit RGB 8-8-8) 1x1: OK
[  200.085144] [U]      Video Output: Frame #002 (select)
[  200.089329] [U]      Video Output: Frame #003 (select)
[  200.093098] [U]      Video Output: Frame #004 (select)
[  200.096844] [U]      Video Output: Frame #005 (select)
[  200.100998] [U]      Video Output: Frame #006 (select)
[  200.104759] [U]      Video Output: Frame #007 (select)
[  200.108913] [U]      Video Output: Frame #008 (select)
[  200.110872] [U]      Video Output: Frame #009 (select)
[  200.112025] [U]
[  200.113496] [U]      Video Capture: Captured 8 buffers
[  200.118262] [U]      AR12 (16-bit ARGB 4-4-4-4) 1x1 -> RGBP (16-bit RGB 5-6-5) 1x1: OK
[  200.155831] [U]      Video Output: Frame #002 (select)
[  200.160021] [U]      Video Output: Frame #003 (select)
[  200.163785] [U]      Video Output: Frame #004 (select)
[  200.167532] [U]      Video Output: Frame #005 (select)
[  200.171854] [U]      Video Output: Frame #006 (select)
[  200.175597] [U]      Video Output: Frame #007 (select)
[  200.179764] [U]      Video Output: Frame #008 (select)
[  200.181727] [U]      Video Output: Frame #009 (select)
[  200.182877] [U]
[  200.184354] [U]      Video Capture: Captured 8 buffers
[  200.189552] [U]      AR12 (16-bit ARGB 4-4-4-4) 1x1 -> AR15 (16-bit ARGB 1-5-5-5) 1x1: OK
[  200.226713] [U]      Video Output: Frame #002 (select)
[  200.230895] [U]      Video Output: Frame #003 (select)
[  200.234668] [U]      Video Output: Frame #004 (select)
[  200.239766] [U]      Video Output: Frame #005 (select)
[  200.243529] [U]      Video Output: Frame #006 (select)
[  200.247253] [U]      Video Output: Frame #007 (select)
[  200.251598] [U]      Video Output: Frame #008 (select)
[  200.253548] [U]      Video Output: Frame #009 (select)
[  200.254697] [U]
[  200.256156] [U]      Video Capture: Captured 8 buffers
[  200.261363] [U]      AR12 (16-bit ARGB 4-4-4-4) 1x1 -> AR12 (16-bit ARGB 4-4-4-4) 1x1: OK
[  200.266028] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  201.257011] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  201.260312] [U]      AR12 (16-bit ARGB 4-4-4-4) 16383x65535 -> BA24 (32-bit ARGB 8-8-8-8) 16383x65535: FAIL
[  201.263677] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  202.253784] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  202.256738] [U]      AR12 (16-bit ARGB 4-4-4-4) 16383x65535 -> RGB3 (24-bit RGB 8-8-8) 16383x65535: FAIL
[  202.260626] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  203.252427] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  203.256851] [U]      AR12 (16-bit ARGB 4-4-4-4) 16383x65535 -> RGBP (16-bit RGB 5-6-5) 16383x65535: FAIL
[  203.269821] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  204.266713] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  204.270659] [U]      AR12 (16-bit ARGB 4-4-4-4) 16383x65535 -> AR15 (16-bit ARGB 1-5-5-5) 16383x65535: FAIL
[  204.274034] stm-dma2d 4002b000.dma2d: dma_alloc_coherent of size 2147323904 failed
[  205.265063] [U]              fail: v4l2-test-buffers.cpp(1349): q.reqbufs(node, 2)
[  205.268019] [U]      AR12 (16-bit ARGB 4-4-4-4) 16383x65535 -> AR12 (16-bit ARGB 4-4-4-4) 16383x65535: FAIL
[  205.389607] [U]      Video Output: Frame #002 (select)
[  205.393699] [U]      Video Output: Frame #003 (select)
[  205.401589] [U]      Video Output: Frame #004 (select)
[  205.411222] [U]      Video Output: Frame #005 (select)
[  205.416545] [U]      Video Output: Frame #006 (select)
[  205.421934] [U]      Video Output: Frame #007 (select)
[  205.427680] [U]      Video Output: Frame #008 (select)
[  205.430785] [U]      Video Output: Frame #009 (select)
[  205.431939] [U]
[  205.433409] [U]      Video Capture: Captured 8 buffers
[  205.443284] [U]      AR12 (16-bit ARGB 4-4-4-4) 240x320 -> BA24 (32-bit ARGB 8-8-8-8) 240x320: OK
[  205.547396] [U]      Video Output: Frame #002 (select)
[  205.553106] [U]      Video Output: Frame #003 (select)
[  205.557856] [U]      Video Output: Frame #004 (select)
[  205.563067] [U]      Video Output: Frame #005 (select)
[  205.567939] [U]      Video Output: Frame #006 (select)
[  205.573170] [U]      Video Output: Frame #007 (select)
[  205.578047] [U]      Video Output: Frame #008 (select)
[  205.581229] [U]      Video Output: Frame #009 (select)
[  205.582360] [U]
[  205.583814] [U]      Video Capture: Captured 8 buffers
[  205.590802] [U]      AR12 (16-bit ARGB 4-4-4-4) 240x320 -> RGB3 (24-bit RGB 8-8-8) 240x320: OK
[  205.673784] [U]      Video Output: Frame #002 (select)
[  205.680126] [U]      Video Output: Frame #003 (select)
[  205.684166] [U]      Video Output: Frame #004 (select)
[  205.689508] [U]      Video Output: Frame #005 (select)
[  205.694186] [U]      Video Output: Frame #006 (select)
[  205.699520] [U]      Video Output: Frame #007 (select)
[  205.704031] [U]      Video Output: Frame #008 (select)
[  205.706640] [U]      Video Output: Frame #009 (select)
[  205.707786] [U]
[  205.709661] [U]      Video Capture: Captured 8 buffers
[  205.716234] [U]      AR12 (16-bit ARGB 4-4-4-4) 240x320 -> RGBP (16-bit RGB 5-6-5) 240x320: OK
[  205.799699] [U]      Video Output: Frame #002 (select)
[  205.804297] [U]      Video Output: Frame #003 (select)
[  205.809609] [U]      Video Output: Frame #004 (select)
[  205.814253] [U]      Video Output: Frame #005 (select)
[  205.819548] [U]      Video Output: Frame #006 (select)
[  205.824186] [U]      Video Output: Frame #007 (select)
[  205.829483] [U]      Video Output: Frame #008 (select)
[  205.832055] [U]      Video Output: Frame #009 (select)
[  205.833181] [U]
[  205.834645] [U]      Video Capture: Captured 8 buffers
[  205.841668] [U]      AR12 (16-bit ARGB 4-4-4-4) 240x320 -> AR15 (16-bit ARGB 1-5-5-5) 240x320: OK
[  205.925108] [U]      Video Output: Frame #002 (select)
[  205.930444] [U]      Video Output: Frame #003 (select)
[  205.935130] [U]      Video Output: Frame #004 (select)
[  205.940509] [U]      Video Output: Frame #005 (select)
[  205.945191] [U]      Video Output: Frame #006 (select)
[  205.950506] [U]      Video Output: Frame #007 (select)
[  205.955182] [U]      Video Output: Frame #008 (select)
[  205.957826] [U]      Video Output: Frame #009 (select)
[  205.959371] [U]
[  205.960829] [U]      Video Capture: Captured 8 buffers
[  205.967428] [U]      AR12 (16-bit ARGB 4-4-4-4) 240x320 -> AR12 (16-bit ARGB 4-4-4-4) 240x320: OK
[  205.977020] [U] Total for stm-dma2d device /dev/video0: 121, Succeeded: 96, Failed: 25, Warnings: 0
*** BLURB HERE ***

Dillon Min (8):
  media: admin-guide: add stm32-dma2d description
  media: dt-bindings: media: add document for STM32 DMA2d bindings
  ARM: dts: stm32: Add DMA2D support for STM32F429 series soc
  ARM: dts: stm32: Enable DMA2D on STM32F469-DISCO board
  media: v4l2-mem2mem: add v4l2_m2m_get_unmapped_area for no-mmu
    platform
  media: v4l2-ctrls: Add RGB color effects control
  clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after
    system enter shell
  media: stm32-dma2d: STM32 DMA2D driver

 .../admin-guide/media/platform-cardlist.rst        |   1 +
 .../devicetree/bindings/media/st,stm32-dma2d.yaml  |  71 ++
 Documentation/userspace-api/media/v4l/control.rst  |   9 +
 arch/arm/boot/dts/stm32f429.dtsi                   |  10 +
 arch/arm/boot/dts/stm32f469-disco.dts              |   4 +
 drivers/clk/clk-stm32f4.c                          |   4 -
 drivers/media/platform/Kconfig                     |   9 +
 drivers/media/platform/Makefile                    |   1 +
 drivers/media/platform/stm32/Makefile              |   2 +
 drivers/media/platform/stm32/dma2d/dma2d-hw.c      | 143 ++++
 drivers/media/platform/stm32/dma2d/dma2d-regs.h    | 113 ++++
 drivers/media/platform/stm32/dma2d/dma2d.c         | 748 +++++++++++++++++++++
 drivers/media/platform/stm32/dma2d/dma2d.h         | 135 ++++
 drivers/media/v4l2-core/v4l2-ctrls-defs.c          |   2 +
 drivers/media/v4l2-core/v4l2-mem2mem.c             |  21 +
 include/media/v4l2-mem2mem.h                       |   5 +
 include/uapi/linux/v4l2-controls.h                 |   4 +-
 17 files changed, 1277 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml
 create mode 100644 drivers/media/platform/stm32/dma2d/dma2d-hw.c
 create mode 100644 drivers/media/platform/stm32/dma2d/dma2d-regs.h
 create mode 100644 drivers/media/platform/stm32/dma2d/dma2d.c
 create mode 100644 drivers/media/platform/stm32/dma2d/dma2d.h

-- 
2.7.4


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From: Dillon Min <redacted>

add stm32-dma2d description for dma2d driver

Signed-off-by: Dillon Min <redacted>
---
v4: no change.

 Documentation/admin-guide/media/platform-cardlist.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/admin-guide/media/platform-cardlist.rst b/Documentation/admin-guide/media/platform-cardlist.rst
index 261e7772eb3e..ac73c4166d1e 100644
--- a/Documentation/admin-guide/media/platform-cardlist.rst
+++ b/Documentation/admin-guide/media/platform-cardlist.rst

@@ -60,6 +60,7 @@ s5p-mfc            Samsung S5P MFC Video Codec
 sh_veu             SuperH VEU mem2mem video processing
 sh_vou             SuperH VOU video output
 stm32-dcmi         STM32 Digital Camera Memory Interface (DCMI)
+stm32-dma2d        STM32 Chrom-Art Accelerator Unit
 sun4i-csi          Allwinner A10 CMOS Sensor Interface Support
 sun6i-csi          Allwinner V3s Camera Sensor Interface
 sun8i-di           Allwinner Deinterlace

-- 
2.7.4


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From: Dillon Min <redacted>

This adds documentation of device tree bindings for the STM32 DMA2D

Signed-off-by: Dillon Min <redacted>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v4: no change.

 .../devicetree/bindings/media/st,stm32-dma2d.yaml  | 71 ++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml

diff --git a/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml b/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml
new file mode 100644
index 000000000000..f97b4a246605
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/st,stm32-dma2d.yaml

@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/st,stm32-dma2d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectronics STM32 Chrom-Art Accelerator DMA2D binding
+
+description:
+  Chrom-ART Accelerator(DMA2D), graphical hardware accelerator
+  enabling enhanced graphical user interface with minimum CPU load
+
+  It can perform the following operations.
+
+  - Filling a part or the whole of a destination image with a specific color.
+  - Copying a part or the whole of a source image into a part or the whole of
+    a destination image.
+  - Copying a part or the whole of a source image into a part or the whole of
+    a destination image with a pixel format conversion.
+  - Blending a part and/or two complete source images with different pixel
+    format and copy the result into a part or the whole of a destination image
+    with a different color format. (TODO)
+
+
+maintainers:
+  - Dillon Min <dillon.minfei@gmail.com>
+
+properties:
+  compatible:
+    const: st,stm32-dma2d
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: dma2d
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/stm32fx-clock.h>
+    #include <dt-bindings/mfd/stm32f4-rcc.h>
+    dma2d: dma2d@4002b000 {
+        compatible = "st,stm32-dma2d";
+        reg = <0x4002b000 0xc00>;
+        interrupts = <90>;
+        resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
+        clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
+        clock-names = "dma2d";
+    };
+
+...

-- 
2.7.4


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From: Dillon Min <redacted>

Add DMA2D for STM32F429 series soc.

Signed-off-by: Dillon Min <redacted>
---
v4: no change.

 arch/arm/boot/dts/stm32f429.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 8748d5850298..1d8be5e7c8b8 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi

@@ -743,6 +743,16 @@
 			st,mem2mem;
 		};
 
+		dma2d: dma2d@4002b000 {
+			compatible = "st,stm32-dma2d";
+			reg = <0x4002b000 0xc00>;
+			interrupts = <90>;
+			resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
+			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
+			clock-names = "dma2d";
+			status = "disabled";
+		};
+
 		mac: ethernet@40028000 {
 			compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 			reg = <0x40028000 0x8000>;

-- 
2.7.4


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From: Dillon Min <redacted>

Enable DMA2D on STM32F469-DISCO board.

Signed-off-by: Dillon Min <redacted>
---
v4: no change.

 arch/arm/boot/dts/stm32f469-disco.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 30905ce672a0..ba26a3375b0d 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts

@@ -132,6 +132,10 @@
 	clock-frequency = <8000000>;
 };
 
+&dma2d {
+	status = "okay";
+};
+
 &dsi {
 	#address-cells = <1>;
 	#size-cells = <0>;

-- 
2.7.4


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From: Dillon Min <redacted>

For platforms without MMU the m2m provides a helper method
v4l2_m2m_get_unmapped_area(), The mmap() routines will call
this to get a proposed address for the mapping.

More detailed information about get_unmapped_area can be found in
Documentation/nommu-mmap.txt

Signed-off-by: Dillon Min <redacted>
---
v4: no change.

 drivers/media/v4l2-core/v4l2-mem2mem.c | 21 +++++++++++++++++++++
 include/media/v4l2-mem2mem.h           |  5 +++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c
index e7f4bf5bc8dd..e2654b422334 100644
--- a/drivers/media/v4l2-core/v4l2-mem2mem.c
+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c

@@ -966,6 +966,27 @@ int v4l2_m2m_mmap(struct file *file, struct v4l2_m2m_ctx *m2m_ctx,
 }
 EXPORT_SYMBOL(v4l2_m2m_mmap);
 
+#ifndef CONFIG_MMU
+unsigned long v4l2_m2m_get_unmapped_area(struct file *file, unsigned long addr,
+					 unsigned long len, unsigned long pgoff,
+					 unsigned long flags)
+{
+	struct v4l2_fh *fh = file->private_data;
+	unsigned long offset = pgoff << PAGE_SHIFT;
+	struct vb2_queue *vq;
+
+	if (offset < DST_QUEUE_OFF_BASE) {
+		vq = v4l2_m2m_get_src_vq(fh->m2m_ctx);
+	} else {
+		vq = v4l2_m2m_get_dst_vq(fh->m2m_ctx);
+		pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
+	}
+
+	return vb2_get_unmapped_area(vq, addr, len, pgoff, flags);
+}
+EXPORT_SYMBOL_GPL(v4l2_m2m_get_unmapped_area);
+#endif
+
 #if defined(CONFIG_MEDIA_CONTROLLER)
 void v4l2_m2m_unregister_media_controller(struct v4l2_m2m_dev *m2m_dev)
 {

diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h
index 5a91b548ecc0..fdbd5257e020 100644
--- a/include/media/v4l2-mem2mem.h
+++ b/include/media/v4l2-mem2mem.h

@@ -495,6 +495,11 @@ __poll_t v4l2_m2m_poll(struct file *file, struct v4l2_m2m_ctx *m2m_ctx,
 int v4l2_m2m_mmap(struct file *file, struct v4l2_m2m_ctx *m2m_ctx,
 		  struct vm_area_struct *vma);
 
+#ifndef CONFIG_MMU
+unsigned long v4l2_m2m_get_unmapped_area(struct file *file, unsigned long addr,
+					 unsigned long len, unsigned long pgoff,
+					 unsigned long flags);
+#endif
 /**
  * v4l2_m2m_init() - initialize per-driver m2m data
  *

-- 
2.7.4


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From: Dillon Min <redacted>

Add V4L2_COLORFX_SET_RGB color effects control, V4L2_CID_COLORFX_RGB
for RGB color setting.

Signed-off-by: Dillon Min <redacted>
---
v4:
- replace V4L2_COLORFX_SET_ARGB, V4L2_CID_COLORFX_ARGB to
  V4L2_COLORFX_SET_RGB, V4L2_CID_COLORFX_RGB since Alpha paramter not used
  in current. thanks Hans.

 Documentation/userspace-api/media/v4l/control.rst | 9 +++++++++
 drivers/media/v4l2-core/v4l2-ctrls-defs.c         | 2 ++
 include/uapi/linux/v4l2-controls.h                | 4 +++-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/userspace-api/media/v4l/control.rst b/Documentation/userspace-api/media/v4l/control.rst
index f8d0b923da20..3eec65174260 100644
--- a/Documentation/userspace-api/media/v4l/control.rst
+++ b/Documentation/userspace-api/media/v4l/control.rst

@@ -242,8 +242,17 @@ Control IDs
     * - ``V4L2_COLORFX_SET_CBCR``
       - The Cb and Cr chroma components are replaced by fixed coefficients
 	determined by ``V4L2_CID_COLORFX_CBCR`` control.
+    * - ``V4L2_COLORFX_SET_RGB``
+      - The RGB components are replaced by the fixed RGB components determined
+        by ``V4L2_CID_COLORFX_RGB`` control.
 
 
+``V4L2_CID_COLORFX_RGB`` ``(integer)``
+    Determines the Red, Green, and Blue coefficients for
+    ``V4L2_COLORFX_SET_RGB`` color effect.
+    Bits [7:0] of the supplied 32 bit value are interpreted as Blue component,
+    bits [15:8] as Green component, bits [23:16] as Red component, and
+    bits [31:24] must be zero.
 
 ``V4L2_CID_COLORFX_CBCR`` ``(integer)``
     Determines the Cb and Cr coefficients for ``V4L2_COLORFX_SET_CBCR``

diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
index 421300e13a41..f4bd90170105 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c

@@ -785,6 +785,7 @@ const char *v4l2_ctrl_get_name(u32 id)
 	case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:	return "Min Number of Output Buffers";
 	case V4L2_CID_ALPHA_COMPONENT:		return "Alpha Component";
 	case V4L2_CID_COLORFX_CBCR:		return "Color Effects, CbCr";
+	case V4L2_CID_COLORFX_RGB:		return "Color Effects, RGB";
 
 	/*
 	 * Codec controls

@@ -1392,6 +1393,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
 		*min = *max = *step = *def = 0;
 		break;
 	case V4L2_CID_BG_COLOR:
+	case V4L2_CID_COLORFX_RGB:
 		*type = V4L2_CTRL_TYPE_INTEGER;
 		*step = 1;
 		*min = 0;

diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index 5532b5f68493..9aa3fd368383 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h

@@ -128,6 +128,7 @@ enum v4l2_colorfx {
 	V4L2_COLORFX_SOLARIZATION		= 13,
 	V4L2_COLORFX_ANTIQUE			= 14,
 	V4L2_COLORFX_SET_CBCR			= 15,
+	V4L2_COLORFX_SET_RGB			= 16,
 };
 #define V4L2_CID_AUTOBRIGHTNESS			(V4L2_CID_BASE+32)
 #define V4L2_CID_BAND_STOP_FILTER		(V4L2_CID_BASE+33)

@@ -145,9 +146,10 @@ enum v4l2_colorfx {
 
 #define V4L2_CID_ALPHA_COMPONENT		(V4L2_CID_BASE+41)
 #define V4L2_CID_COLORFX_CBCR			(V4L2_CID_BASE+42)
+#define V4L2_CID_COLORFX_RGB			(V4L2_CID_BASE+43)
 
 /* last CID + 1 */
-#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+43)
+#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+44)
 
 /* USER-class private control IDs */
 

-- 
2.7.4


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On 14/10/2021 12:25, dillon.minfei@gmail.com wrote:

Can you make another small change here? Please change:

	*max = 0xFFFFFF;

to:

	*max = 0xffffff;

to keep in line with the coding standard for hex values.

Also, can you add a separate patch that adds an entry here for V4L2_CID_COLORFX_CBCR
that sets *max to 0xffff? I noticed that that was missing. While adding V4L2_CID_COLORFX_RGB
it's good to fix V4L2_CID_COLORFX_CBCR as well.

Regards,

	Hans

_______________________________________________
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Hi Hans

Thanks for quick reply

On Thu, 14 Oct 2021 at 18:44, Hans Verkuil [off-list ref] wrote:

On 14/10/2021 12:25, dillon.minfei@gmail.com wrote:

quoted

From: Dillon Min <redacted>

Add V4L2_COLORFX_SET_RGB color effects control, V4L2_CID_COLORFX_RGB
for RGB color setting.

Signed-off-by: Dillon Min <redacted>
---
v4:
- replace V4L2_COLORFX_SET_ARGB, V4L2_CID_COLORFX_ARGB to
  V4L2_COLORFX_SET_RGB, V4L2_CID_COLORFX_RGB since Alpha paramter not used
  in current. thanks Hans.

 Documentation/userspace-api/media/v4l/control.rst | 9 +++++++++
 drivers/media/v4l2-core/v4l2-ctrls-defs.c         | 2 ++
 include/uapi/linux/v4l2-controls.h                | 4 +++-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/userspace-api/media/v4l/control.rst b/Documentation/userspace-api/media/v4l/control.rst
index f8d0b923da20..3eec65174260 100644
--- a/Documentation/userspace-api/media/v4l/control.rst
+++ b/Documentation/userspace-api/media/v4l/control.rst

@@ -242,8 +242,17 @@ Control IDs
     * - ``V4L2_COLORFX_SET_CBCR``
       - The Cb and Cr chroma components are replaced by fixed coefficients
      determined by ``V4L2_CID_COLORFX_CBCR`` control.
+    * - ``V4L2_COLORFX_SET_RGB``
+      - The RGB components are replaced by the fixed RGB components determined
+        by ``V4L2_CID_COLORFX_RGB`` control.


+``V4L2_CID_COLORFX_RGB`` ``(integer)``
+    Determines the Red, Green, and Blue coefficients for
+    ``V4L2_COLORFX_SET_RGB`` color effect.
+    Bits [7:0] of the supplied 32 bit value are interpreted as Blue component,
+    bits [15:8] as Green component, bits [23:16] as Red component, and
+    bits [31:24] must be zero.

 ``V4L2_CID_COLORFX_CBCR`` ``(integer)``
     Determines the Cb and Cr coefficients for ``V4L2_COLORFX_SET_CBCR``

diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
index 421300e13a41..f4bd90170105 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c

@@ -785,6 +785,7 @@ const char *v4l2_ctrl_get_name(u32 id)
      case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:   return "Min Number of Output Buffers";
      case V4L2_CID_ALPHA_COMPONENT:          return "Alpha Component";
      case V4L2_CID_COLORFX_CBCR:             return "Color Effects, CbCr";
+     case V4L2_CID_COLORFX_RGB:              return "Color Effects, RGB";

      /*
       * Codec controls

@@ -1392,6 +1393,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
              *min = *max = *step = *def = 0;
              break;
      case V4L2_CID_BG_COLOR:
+     case V4L2_CID_COLORFX_RGB:
              *type = V4L2_CTRL_TYPE_INTEGER;
              *step = 1;
              *min = 0;

Can you make another small change here? Please change:

        *max = 0xFFFFFF;

to:

        *max = 0xffffff;

to keep in line with the coding standard for hex values.

Sure, do it right now.

Also, can you add a separate patch that adds an entry here for V4L2_CID_COLORFX_CBCR
that sets *max to 0xffff? I noticed that that was missing. While adding V4L2_CID_COLORFX_RGB
it's good to fix V4L2_CID_COLORFX_CBCR as well.

Sure, you mean the final code like this? first patch to fix cbcr 0xFFFFFF,
another one to add V4L2_CID_COLORFX_RGB entry.

1395         case V4L2_CID_BG_COLOR:
1396         case V4L2_CID_COLORFX_RGB:
1397                 *type = V4L2_CTRL_TYPE_INTEGER;
1398                 *step = 1;
1399                 *min = 0;
1400                 /* Max is calculated as RGB888 that is 2^24 */
1401                 *max = 0xffffff;
1402                 break;

Best Regards
Dillon

Regards,

        Hans

quoted

diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index 5532b5f68493..9aa3fd368383 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h

@@ -128,6 +128,7 @@ enum v4l2_colorfx {
      V4L2_COLORFX_SOLARIZATION               = 13,
      V4L2_COLORFX_ANTIQUE                    = 14,
      V4L2_COLORFX_SET_CBCR                   = 15,
+     V4L2_COLORFX_SET_RGB                    = 16,
 };
 #define V4L2_CID_AUTOBRIGHTNESS                      (V4L2_CID_BASE+32)
 #define V4L2_CID_BAND_STOP_FILTER            (V4L2_CID_BASE+33)

@@ -145,9 +146,10 @@ enum v4l2_colorfx {

 #define V4L2_CID_ALPHA_COMPONENT             (V4L2_CID_BASE+41)
 #define V4L2_CID_COLORFX_CBCR                        (V4L2_CID_BASE+42)
+#define V4L2_CID_COLORFX_RGB                 (V4L2_CID_BASE+43)

 /* last CID + 1 */
-#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+43)
+#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+44)

 /* USER-class private control IDs */

_______________________________________________
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On 14/10/2021 12:53, Dillon Min wrote:

Hi Hans

Thanks for quick reply

On Thu, 14 Oct 2021 at 18:44, Hans Verkuil [off-list ref] wrote:

quoted

On 14/10/2021 12:25, dillon.minfei@gmail.com wrote:

quoted

From: Dillon Min <redacted>

Add V4L2_COLORFX_SET_RGB color effects control, V4L2_CID_COLORFX_RGB
for RGB color setting.

Signed-off-by: Dillon Min <redacted>
---
v4:
- replace V4L2_COLORFX_SET_ARGB, V4L2_CID_COLORFX_ARGB to
  V4L2_COLORFX_SET_RGB, V4L2_CID_COLORFX_RGB since Alpha paramter not used
  in current. thanks Hans.

 Documentation/userspace-api/media/v4l/control.rst | 9 +++++++++
 drivers/media/v4l2-core/v4l2-ctrls-defs.c         | 2 ++
 include/uapi/linux/v4l2-controls.h                | 4 +++-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/userspace-api/media/v4l/control.rst b/Documentation/userspace-api/media/v4l/control.rst
index f8d0b923da20..3eec65174260 100644
--- a/Documentation/userspace-api/media/v4l/control.rst
+++ b/Documentation/userspace-api/media/v4l/control.rst

@@ -242,8 +242,17 @@ Control IDs
     * - ``V4L2_COLORFX_SET_CBCR``
       - The Cb and Cr chroma components are replaced by fixed coefficients
      determined by ``V4L2_CID_COLORFX_CBCR`` control.
+    * - ``V4L2_COLORFX_SET_RGB``
+      - The RGB components are replaced by the fixed RGB components determined
+        by ``V4L2_CID_COLORFX_RGB`` control.


+``V4L2_CID_COLORFX_RGB`` ``(integer)``
+    Determines the Red, Green, and Blue coefficients for
+    ``V4L2_COLORFX_SET_RGB`` color effect.
+    Bits [7:0] of the supplied 32 bit value are interpreted as Blue component,
+    bits [15:8] as Green component, bits [23:16] as Red component, and
+    bits [31:24] must be zero.

 ``V4L2_CID_COLORFX_CBCR`` ``(integer)``
     Determines the Cb and Cr coefficients for ``V4L2_COLORFX_SET_CBCR``

diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
index 421300e13a41..f4bd90170105 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c

@@ -785,6 +785,7 @@ const char *v4l2_ctrl_get_name(u32 id)
      case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:   return "Min Number of Output Buffers";
      case V4L2_CID_ALPHA_COMPONENT:          return "Alpha Component";
      case V4L2_CID_COLORFX_CBCR:             return "Color Effects, CbCr";
+     case V4L2_CID_COLORFX_RGB:              return "Color Effects, RGB";

      /*
       * Codec controls

@@ -1392,6 +1393,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
              *min = *max = *step = *def = 0;
              break;
      case V4L2_CID_BG_COLOR:
+     case V4L2_CID_COLORFX_RGB:
              *type = V4L2_CTRL_TYPE_INTEGER;
              *step = 1;
              *min = 0;

Can you make another small change here? Please change:

        *max = 0xFFFFFF;

to:

        *max = 0xffffff;

to keep in line with the coding standard for hex values.

Sure, do it right now.

quoted

Also, can you add a separate patch that adds an entry here for V4L2_CID_COLORFX_CBCR
that sets *max to 0xffff? I noticed that that was missing. While adding V4L2_CID_COLORFX_RGB
it's good to fix V4L2_CID_COLORFX_CBCR as well.

Sure, you mean the final code like this? first patch to fix cbcr 0xFFFFFF,

For cbcr max should be 0xffff.

another one to add V4L2_CID_COLORFX_RGB entry.

1395         case V4L2_CID_BG_COLOR:
1396         case V4L2_CID_COLORFX_RGB:
1397                 *type = V4L2_CTRL_TYPE_INTEGER;
1398                 *step = 1;
1399                 *min = 0;
1400                 /* Max is calculated as RGB888 that is 2^24 */

Actually, the comment is wrong: it should be 2^24-1. Let's fix that too.

1401                 *max = 0xffffff;

Yes, that's what I am looking for.

Regards,

	Hans

1402                 break;

Best Regards
Dillon

quoted

Regards,

        Hans

quoted

diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index 5532b5f68493..9aa3fd368383 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h

@@ -128,6 +128,7 @@ enum v4l2_colorfx {
      V4L2_COLORFX_SOLARIZATION               = 13,
      V4L2_COLORFX_ANTIQUE                    = 14,
      V4L2_COLORFX_SET_CBCR                   = 15,
+     V4L2_COLORFX_SET_RGB                    = 16,
 };
 #define V4L2_CID_AUTOBRIGHTNESS                      (V4L2_CID_BASE+32)
 #define V4L2_CID_BAND_STOP_FILTER            (V4L2_CID_BASE+33)

@@ -145,9 +146,10 @@ enum v4l2_colorfx {

 #define V4L2_CID_ALPHA_COMPONENT             (V4L2_CID_BASE+41)
 #define V4L2_CID_COLORFX_CBCR                        (V4L2_CID_BASE+42)
+#define V4L2_CID_COLORFX_RGB                 (V4L2_CID_BASE+43)

 /* last CID + 1 */
-#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+43)
+#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+44)

 /* USER-class private control IDs */

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On Thu, 14 Oct 2021 at 19:22, Hans Verkuil [off-list ref] wrote:

On 14/10/2021 12:53, Dillon Min wrote:

quoted

Hi Hans

Thanks for quick reply

On Thu, 14 Oct 2021 at 18:44, Hans Verkuil [off-list ref] wrote:

quoted

On 14/10/2021 12:25, dillon.minfei@gmail.com wrote:

quoted

From: Dillon Min <redacted>

Add V4L2_COLORFX_SET_RGB color effects control, V4L2_CID_COLORFX_RGB
for RGB color setting.

Signed-off-by: Dillon Min <redacted>
---
v4:
- replace V4L2_COLORFX_SET_ARGB, V4L2_CID_COLORFX_ARGB to
  V4L2_COLORFX_SET_RGB, V4L2_CID_COLORFX_RGB since Alpha paramter not used
  in current. thanks Hans.

 Documentation/userspace-api/media/v4l/control.rst | 9 +++++++++
 drivers/media/v4l2-core/v4l2-ctrls-defs.c         | 2 ++
 include/uapi/linux/v4l2-controls.h                | 4 +++-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/userspace-api/media/v4l/control.rst b/Documentation/userspace-api/media/v4l/control.rst
index f8d0b923da20..3eec65174260 100644
--- a/Documentation/userspace-api/media/v4l/control.rst
+++ b/Documentation/userspace-api/media/v4l/control.rst

@@ -242,8 +242,17 @@ Control IDs
     * - ``V4L2_COLORFX_SET_CBCR``
       - The Cb and Cr chroma components are replaced by fixed coefficients
      determined by ``V4L2_CID_COLORFX_CBCR`` control.
+    * - ``V4L2_COLORFX_SET_RGB``
+      - The RGB components are replaced by the fixed RGB components determined
+        by ``V4L2_CID_COLORFX_RGB`` control.


+``V4L2_CID_COLORFX_RGB`` ``(integer)``
+    Determines the Red, Green, and Blue coefficients for
+    ``V4L2_COLORFX_SET_RGB`` color effect.
+    Bits [7:0] of the supplied 32 bit value are interpreted as Blue component,
+    bits [15:8] as Green component, bits [23:16] as Red component, and
+    bits [31:24] must be zero.

 ``V4L2_CID_COLORFX_CBCR`` ``(integer)``
     Determines the Cb and Cr coefficients for ``V4L2_COLORFX_SET_CBCR``

diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c
index 421300e13a41..f4bd90170105 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c

@@ -785,6 +785,7 @@ const char *v4l2_ctrl_get_name(u32 id)
      case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT:   return "Min Number of Output Buffers";
      case V4L2_CID_ALPHA_COMPONENT:          return "Alpha Component";
      case V4L2_CID_COLORFX_CBCR:             return "Color Effects, CbCr";
+     case V4L2_CID_COLORFX_RGB:              return "Color Effects, RGB";

      /*
       * Codec controls

@@ -1392,6 +1393,7 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
              *min = *max = *step = *def = 0;
              break;
      case V4L2_CID_BG_COLOR:
+     case V4L2_CID_COLORFX_RGB:
              *type = V4L2_CTRL_TYPE_INTEGER;
              *step = 1;
              *min = 0;

Can you make another small change here? Please change:

        *max = 0xFFFFFF;

to:

        *max = 0xffffff;

to keep in line with the coding standard for hex values.

Sure, do it right now.

quoted

Also, can you add a separate patch that adds an entry here for V4L2_CID_COLORFX_CBCR
that sets *max to 0xffff? I noticed that that was missing. While adding V4L2_CID_COLORFX_RGB
it's good to fix V4L2_CID_COLORFX_CBCR as well.

Sure, you mean the final code like this? first patch to fix cbcr 0xFFFFFF,

For cbcr max should be 0xffff.

Sure.

quoted

another one to add V4L2_CID_COLORFX_RGB entry.

1395         case V4L2_CID_BG_COLOR:
1396         case V4L2_CID_COLORFX_RGB:
1397                 *type = V4L2_CTRL_TYPE_INTEGER;
1398                 *step = 1;
1399                 *min = 0;
1400                 /* Max is calculated as RGB888 that is 2^24 */

Actually, the comment is wrong: it should be 2^24-1. Let's fix that too.

Okay.

quoted

1401                 *max = 0xffffff;

Yes, that's what I am looking for.

Regards,

        Hans

quoted

1402                 break;

Best Regards
Dillon

quoted

Regards,

        Hans

quoted

diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index 5532b5f68493..9aa3fd368383 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h

@@ -128,6 +128,7 @@ enum v4l2_colorfx {
      V4L2_COLORFX_SOLARIZATION               = 13,
      V4L2_COLORFX_ANTIQUE                    = 14,
      V4L2_COLORFX_SET_CBCR                   = 15,
+     V4L2_COLORFX_SET_RGB                    = 16,
 };
 #define V4L2_CID_AUTOBRIGHTNESS                      (V4L2_CID_BASE+32)
 #define V4L2_CID_BAND_STOP_FILTER            (V4L2_CID_BASE+33)

@@ -145,9 +146,10 @@ enum v4l2_colorfx {

 #define V4L2_CID_ALPHA_COMPONENT             (V4L2_CID_BASE+41)
 #define V4L2_CID_COLORFX_CBCR                        (V4L2_CID_BASE+42)
+#define V4L2_CID_COLORFX_RGB                 (V4L2_CID_BASE+43)

 /* last CID + 1 */
-#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+43)
+#define V4L2_CID_LASTP1                         (V4L2_CID_BASE+44)

 /* USER-class private control IDs */

Best Regards.
Dillon

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From: Dillon Min <redacted>

stm32's clk driver register two ltdc gate clk to clk core by
clk_hw_register_gate() and clk_hw_register_composite()

first: 'stm32f429_gates[]', clk name is 'ltdc', which no user to use.
second: 'stm32f429_aux_clk[]', clk name is 'lcd-tft', used by ltdc driver

both of them point to the same offset of stm32's RCC register. after
kernel enter console, clk core turn off ltdc's clk as 'stm32f429_gates[]'
is no one to use. but, actually 'stm32f429_aux_clk[]' is in use.

stm32f469/746/769 have the same issue, fix it.

Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock")
Signed-off-by: Dillon Min <redacted>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/linux-arm-kernel/1590564453-24499-7-git-send-email-dillon.minfei@gmail.com/
Link: https://lore.kernel.org/lkml/CAPTRvHkf0cK_4ZidM17rPo99gWDmxgqFt4CDUjqFFwkOeQeFDg@mail.gmail.com/
Signed-off-by: Dillon Min <redacted>
---
v4: no change.

 drivers/clk/clk-stm32f4.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index af46176ad053..473dfe632cc5 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c

@@ -129,7 +129,6 @@ static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
 	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
-	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
 };
 
 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {

@@ -211,7 +210,6 @@ static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
 	{ STM32F4_RCC_APB2ENR, 20,	"spi5",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
-	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
 };
 
 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {

@@ -286,7 +284,6 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },
-	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
 };
 
 static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {

@@ -364,7 +361,6 @@ static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
 	{ STM32F4_RCC_APB2ENR, 21,	"spi6",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 22,	"sai1",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 23,	"sai2",		"apb2_div" },
-	{ STM32F4_RCC_APB2ENR, 26,	"ltdc",		"apb2_div" },
 	{ STM32F4_RCC_APB2ENR, 30,	"mdio",		"apb2_div" },
 };
 

-- 
2.7.4


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From: Dillon Min <redacted>

This V4L2 subdev m2m driver enables Chrom-Art Accelerator unit
of STMicroelectronics STM32 SoC series.

Currently support r2m, m2m, m2m_pfc functions.
- r2m, Filling a part or the whole of a destination image with a specific
  color.
- m2m, Copying a part or the whole of a source image into a part or the
  whole of a destination.
- m2m_pfc, Copying a part or the whole of a source image into a part or the
  whole of a destination image with a pixel format conversion.

Signed-off-by: Dillon Min <redacted>
---
v4:
- replace V4L2_COLORFX_SET_ARGB, V4L2_CID_COLORFX_ARGB to
  V4L2_COLORFX_SET_RGB, V4L2_CID_COLORFX_RGB since Alpha paramter not used
  in current. thanks Hans.

 drivers/media/platform/Kconfig                  |   9 +
 drivers/media/platform/Makefile                 |   1 +
 drivers/media/platform/stm32/Makefile           |   2 +
 drivers/media/platform/stm32/dma2d/dma2d-hw.c   | 143 +++++
 drivers/media/platform/stm32/dma2d/dma2d-regs.h | 113 ++++
 drivers/media/platform/stm32/dma2d/dma2d.c      | 748 ++++++++++++++++++++++++
 drivers/media/platform/stm32/dma2d/dma2d.h      | 135 +++++
 7 files changed, 1151 insertions(+)
 create mode 100644 drivers/media/platform/stm32/dma2d/dma2d-hw.c
 create mode 100644 drivers/media/platform/stm32/dma2d/dma2d-regs.h
 create mode 100644 drivers/media/platform/stm32/dma2d/dma2d.c
 create mode 100644 drivers/media/platform/stm32/dma2d/dma2d.h

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 157c924686e4..4df18623e4ad 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig

@@ -473,6 +473,15 @@ config VIDEO_STI_DELTA_DRIVER
 
 endif # VIDEO_STI_DELTA
 
+config VIDEO_STM32_DMA2D
+	tristate "STM32 Chrom-Art Accelerator (DMA2D)"
+	depends on (VIDEO_DEV && VIDEO_V4L2 && ARCH_STM32) || COMPILE_TEST
+	select VIDEOBUF2_DMA_CONTIG
+	select V4L2_MEM2MEM_DEV
+	help
+	  The STM32 DMA2D is a memory-to-memory engine for pixel conversion
+	  and specialized DMA dedicated to image manipulation.
+
 config VIDEO_RENESAS_FDP1
 	tristate "Renesas Fine Display Processor"
 	depends on VIDEO_DEV && VIDEO_V4L2

diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 73ce083c2fc6..46f1c05bc576 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile

@@ -70,6 +70,7 @@ obj-$(CONFIG_VIDEO_ATMEL_ISI)		+= atmel/
 obj-$(CONFIG_VIDEO_ATMEL_XISC)		+= atmel/
 
 obj-$(CONFIG_VIDEO_STM32_DCMI)		+= stm32/
+obj-$(CONFIG_VIDEO_STM32_DMA2D)		+= stm32/
 
 obj-$(CONFIG_VIDEO_MEDIATEK_VPU)	+= mtk-vpu/
 

diff --git a/drivers/media/platform/stm32/Makefile b/drivers/media/platform/stm32/Makefile
index 48b36db2c2e2..896ef98a73ab 100644
--- a/drivers/media/platform/stm32/Makefile
+++ b/drivers/media/platform/stm32/Makefile

@@ -1,2 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32-dcmi.o
+stm32-dma2d-objs := dma2d/dma2d.o dma2d/dma2d-hw.o
+obj-$(CONFIG_VIDEO_STM32_DMA2D) += stm32-dma2d.o

diff --git a/drivers/media/platform/stm32/dma2d/dma2d-hw.c b/drivers/media/platform/stm32/dma2d/dma2d-hw.c
new file mode 100644
index 000000000000..8c1c664ab13b
--- /dev/null
+++ b/drivers/media/platform/stm32/dma2d/dma2d-hw.c

@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver
+ *
+ * Copyright (c) 2021 Dillon Min
+ * Dillon Min, <dillon.minfei@gmail.com>
+ *
+ * based on s5p-g2d
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Kamil Debski, <k.debski@samsung.com>
+ */
+
+#include <linux/io.h>
+
+#include "dma2d.h"
+#include "dma2d-regs.h"
+
+static inline u32 reg_read(void __iomem *base, u32 reg)
+{
+	return readl_relaxed(base + reg);
+}
+
+static inline void reg_write(void __iomem *base, u32 reg, u32 val)
+{
+	writel_relaxed(val, base + reg);
+}
+
+static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
+{
+	reg_write(base, reg, reg_read(base, reg) | mask);
+}
+
+static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
+{
+	reg_write(base, reg, reg_read(base, reg) & ~mask);
+}
+
+static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
+				   u32 val)
+{
+	reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
+}
+
+void dma2d_start(struct dma2d_dev *d)
+{
+	reg_update_bits(d->regs, DMA2D_CR_REG, CR_START, CR_START);
+}
+
+u32 dma2d_get_int(struct dma2d_dev *d)
+{
+	return reg_read(d->regs, DMA2D_ISR_REG);
+}
+
+void dma2d_clear_int(struct dma2d_dev *d)
+{
+	u32 isr_val = reg_read(d->regs, DMA2D_ISR_REG);
+
+	reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f);
+}
+
+void dma2d_config_common(struct dma2d_dev *d, enum dma2d_op_mode op_mode,
+			 u16 width, u16 height)
+{
+	reg_update_bits(d->regs, DMA2D_CR_REG, CR_MODE_MASK,
+			op_mode << CR_MODE_SHIFT);
+
+	reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height);
+}
+
+void dma2d_config_out(struct dma2d_dev *d, struct dma2d_frame *frm,
+		      dma_addr_t o_addr)
+{
+	reg_update_bits(d->regs, DMA2D_CR_REG, CR_CEIE, CR_CEIE);
+	reg_update_bits(d->regs, DMA2D_CR_REG, CR_CTCIE, CR_CTCIE);
+	reg_update_bits(d->regs, DMA2D_CR_REG, CR_CAEIE, CR_CAEIE);
+	reg_update_bits(d->regs, DMA2D_CR_REG, CR_TCIE, CR_TCIE);
+	reg_update_bits(d->regs, DMA2D_CR_REG, CR_TEIE, CR_TEIE);
+
+	if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
+	    frm->fmt->cmode <= CM_MODE_ARGB4444)
+		reg_update_bits(d->regs, DMA2D_OPFCCR_REG, OPFCCR_CM_MASK,
+				frm->fmt->cmode);
+
+	reg_write(d->regs, DMA2D_OMAR_REG, o_addr);
+
+	reg_write(d->regs, DMA2D_OCOLR_REG,
+		  (frm->a_rgb[3] << 24) |
+		  (frm->a_rgb[2] << 16) |
+		  (frm->a_rgb[1] << 8) |
+		  frm->a_rgb[0]);
+
+	reg_update_bits(d->regs, DMA2D_OOR_REG, OOR_LO_MASK,
+			frm->line_offset & 0x3fff);
+}
+
+void dma2d_config_fg(struct dma2d_dev *d, struct dma2d_frame *frm,
+		     dma_addr_t f_addr)
+{
+	reg_write(d->regs, DMA2D_FGMAR_REG, f_addr);
+	reg_update_bits(d->regs, DMA2D_FGOR_REG, FGOR_LO_MASK,
+			frm->line_offset);
+
+	if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
+	    frm->fmt->cmode <= CM_MODE_A4)
+		reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_CM_MASK,
+				frm->fmt->cmode);
+
+	reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_AM_MASK,
+			(frm->a_mode << 16) & 0x03);
+
+	reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_ALPHA_MASK,
+			frm->a_rgb[3] << 24);
+
+	reg_write(d->regs, DMA2D_FGCOLR_REG,
+		  (frm->a_rgb[2] << 16) |
+		  (frm->a_rgb[1] << 8) |
+		  frm->a_rgb[0]);
+}
+
+void dma2d_config_bg(struct dma2d_dev *d, struct dma2d_frame *frm,
+		     dma_addr_t b_addr)
+{
+	reg_write(d->regs, DMA2D_BGMAR_REG, b_addr);
+	reg_update_bits(d->regs, DMA2D_BGOR_REG, BGOR_LO_MASK,
+			frm->line_offset);
+
+	if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
+	    frm->fmt->cmode <= CM_MODE_A4)
+		reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_CM_MASK,
+				frm->fmt->cmode);
+
+	reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_AM_MASK,
+			(frm->a_mode << 16) & 0x03);
+
+	reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_ALPHA_MASK,
+			frm->a_rgb[3] << 24);
+
+	reg_write(d->regs, DMA2D_BGCOLR_REG,
+		  (frm->a_rgb[2] << 16) |
+		  (frm->a_rgb[1] << 8) |
+		  frm->a_rgb[0]);
+}

diff --git a/drivers/media/platform/stm32/dma2d/dma2d-regs.h b/drivers/media/platform/stm32/dma2d/dma2d-regs.h
new file mode 100644
index 000000000000..2128364406c8
--- /dev/null
+++ b/drivers/media/platform/stm32/dma2d/dma2d-regs.h

@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver
+ *
+ * Copyright (c) 2021 Dillon Min
+ * Dillon Min, <dillon.minfei@gmail.com>
+ *
+ * based on s5p-g2d
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Kamil Debski, <k.debski@samsung.com>
+ */
+
+#ifndef __DMA2D_REGS_H__
+#define __DMA2D_REGS_H__
+
+#define DMA2D_CR_REG		0x0000
+#define CR_MODE_MASK		GENMASK(17, 16)
+#define CR_MODE_SHIFT		16
+#define CR_M2M			0x0000
+#define CR_M2M_PFC		BIT(16)
+#define CR_M2M_BLEND		BIT(17)
+#define CR_R2M			(BIT(17) | BIT(16))
+#define CR_CEIE			BIT(13)
+#define CR_CTCIE		BIT(12)
+#define CR_CAEIE		BIT(11)
+#define CR_TWIE			BIT(10)
+#define CR_TCIE			BIT(9)
+#define CR_TEIE			BIT(8)
+#define CR_ABORT		BIT(2)
+#define CR_SUSP			BIT(1)
+#define CR_START		BIT(0)
+
+#define DMA2D_ISR_REG		0x0004
+#define ISR_CEIF		BIT(5)
+#define ISR_CTCIF		BIT(4)
+#define ISR_CAEIF		BIT(3)
+#define ISR_TWIF		BIT(2)
+#define ISR_TCIF		BIT(1)
+#define ISR_TEIF		BIT(0)
+
+#define DMA2D_IFCR_REG		0x0008
+#define IFCR_CCEIF		BIT(5)
+#define IFCR_CCTCIF		BIT(4)
+#define IFCR_CAECIF		BIT(3)
+#define IFCR_CTWIF		BIT(2)
+#define IFCR_CTCIF		BIT(1)
+#define IFCR_CTEIF		BIT(0)
+
+#define DMA2D_FGMAR_REG		0x000c
+#define DMA2D_FGOR_REG		0x0010
+#define FGOR_LO_MASK		GENMASK(13, 0)
+
+#define DMA2D_BGMAR_REG		0x0014
+#define DMA2D_BGOR_REG		0x0018
+#define BGOR_LO_MASK		GENMASK(13, 0)
+
+#define DMA2D_FGPFCCR_REG	0x001c
+#define FGPFCCR_ALPHA_MASK	GENMASK(31, 24)
+#define FGPFCCR_AM_MASK		GENMASK(17, 16)
+#define FGPFCCR_CS_MASK		GENMASK(15, 8)
+#define FGPFCCR_START		BIT(5)
+#define FGPFCCR_CCM_RGB888	BIT(4)
+#define FGPFCCR_CM_MASK		GENMASK(3, 0)
+
+#define DMA2D_FGCOLR_REG	0x0020
+#define FGCOLR_REG_MASK		GENMASK(23, 16)
+#define FGCOLR_GREEN_MASK	GENMASK(15, 8)
+#define FGCOLR_BLUE_MASK	GENMASK(7, 0)
+
+#define DMA2D_BGPFCCR_REG	0x0024
+#define BGPFCCR_ALPHA_MASK	GENMASK(31, 24)
+#define BGPFCCR_AM_MASK		GENMASK(17, 16)
+#define BGPFCCR_CS_MASK		GENMASK(15, 8)
+#define BGPFCCR_START		BIT(5)
+#define BGPFCCR_CCM_RGB888	BIT(4)
+#define BGPFCCR_CM_MASK		GENMASK(3, 0)
+
+#define DMA2D_BGCOLR_REG	0x0028
+#define BGCOLR_REG_MASK		GENMASK(23, 16)
+#define BGCOLR_GREEN_MASK	GENMASK(15, 8)
+#define BGCOLR_BLUE_MASK	GENMASK(7, 0)
+
+#define DMA2D_OPFCCR_REG	0x0034
+#define OPFCCR_CM_MASK		GENMASK(2, 0)
+
+#define DMA2D_OCOLR_REG		0x0038
+#define OCOLR_ALPHA_MASK	GENMASK(31, 24)
+#define OCOLR_RED_MASK		GENMASK(23, 16)
+#define OCOLR_GREEN_MASK	GENMASK(15, 8)
+#define OCOLR_BLUE_MASK		GENMASK(7, 0)
+
+#define DMA2D_OMAR_REG		0x003c
+
+#define DMA2D_OOR_REG		0x0040
+#define OOR_LO_MASK		GENMASK(13, 0)
+
+#define DMA2D_NLR_REG		0x0044
+#define NLR_PL_MASK		GENMASK(29, 16)
+#define NLR_NL_MASK		GENMASK(15, 0)
+
+/* Hardware limits */
+#define MAX_WIDTH		0x3fff
+#define MAX_HEIGHT		0xffff
+
+#define DEFAULT_WIDTH		240
+#define DEFAULT_HEIGHT		320
+#define DEFAULT_SIZE		307200
+
+#define CM_MODE_ARGB8888	0x00
+#define CM_MODE_ARGB4444	0x04
+#define CM_MODE_A4		0x0a
+#endif /* __DMA2D_REGS_H__ */

diff --git a/drivers/media/platform/stm32/dma2d/dma2d.c b/drivers/media/platform/stm32/dma2d/dma2d.c
new file mode 100644
index 000000000000..7cef00133686
--- /dev/null
+++ b/drivers/media/platform/stm32/dma2d/dma2d.c

@@ -0,0 +1,748 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * STM32 DMA2D - 2D Graphics Accelerator Driver
+ *
+ * Copyright (c) 2021 Dillon Min
+ * Dillon Min, <dillon.minfei@gmail.com>
+ *
+ * based on s5p-g2d
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * Kamil Debski, <k.debski@samsung.com>
+ */
+
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/timer.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+
+#include <linux/platform_device.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-event.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "dma2d.h"
+#include "dma2d-regs.h"
+
+/*
+ * This V4L2 subdev m2m driver enables Chrom-Art Accelerator unit
+ * of STMicroelectronics STM32 SoC series.
+ *
+ * Currently support r2m, m2m, m2m_pfc.
+ *
+ * - r2m, Filling a part or the whole of a destination image with a specific
+ *   color.
+ * - m2m, Copying a part or the whole of a source image into a part or the
+ *   whole of a destination.
+ * - m2m_pfc, Copying a part or the whole of a source image into a part or the
+ *   whole of a destination image with a pixel format conversion.
+ */
+
+#define fh2ctx(__fh) container_of(__fh, struct dma2d_ctx, fh)
+
+static const struct dma2d_fmt formats[] = {
+	{
+		.fourcc	= V4L2_PIX_FMT_ARGB32,
+		.cmode = DMA2D_CMODE_ARGB8888,
+		.depth = 32,
+	},
+	{
+		.fourcc	= V4L2_PIX_FMT_RGB24,
+		.cmode = DMA2D_CMODE_RGB888,
+		.depth = 24,
+	},
+	{
+		.fourcc	= V4L2_PIX_FMT_RGB565,
+		.cmode = DMA2D_CMODE_RGB565,
+		.depth = 16,
+	},
+	{
+		.fourcc	= V4L2_PIX_FMT_ARGB555,
+		.cmode = DMA2D_CMODE_ARGB1555,
+		.depth = 16,
+	},
+	{
+		.fourcc	= V4L2_PIX_FMT_ARGB444,
+		.cmode = DMA2D_CMODE_ARGB4444,
+		.depth = 16,
+	},
+};
+
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+static const struct dma2d_frame def_frame = {
+	.width		= DEFAULT_WIDTH,
+	.height		= DEFAULT_HEIGHT,
+	.line_offset	= 0,
+	.a_rgb		= {0x00, 0x00, 0x00, 0xff},
+	.a_mode		= DMA2D_ALPHA_MODE_NO_MODIF,
+	.fmt		= (struct dma2d_fmt *)&formats[0],
+	.size		= DEFAULT_SIZE,
+};
+
+static struct dma2d_fmt *find_fmt(int pixelformat)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_FORMATS; i++) {
+		if (formats[i].fourcc == pixelformat)
+			return (struct dma2d_fmt *)&formats[i];
+	}
+
+	return NULL;
+}
+
+static struct dma2d_frame *get_frame(struct dma2d_ctx *ctx,
+				     enum v4l2_buf_type type)
+{
+	return V4L2_TYPE_IS_OUTPUT(type) ? &ctx->cap : &ctx->out;
+}
+
+static int dma2d_queue_setup(struct vb2_queue *vq,
+			     unsigned int *nbuffers, unsigned int *nplanes,
+			     unsigned int sizes[], struct device *alloc_devs[])
+{
+	struct dma2d_ctx *ctx = vb2_get_drv_priv(vq);
+	struct dma2d_frame *f = get_frame(ctx, vq->type);
+
+	if (*nplanes)
+		return sizes[0] < f->size ? -EINVAL : 0;
+
+	sizes[0] = f->size;
+	*nplanes = 1;
+
+	return 0;
+}
+
+static int dma2d_buf_out_validate(struct vb2_buffer *vb)
+{
+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+
+	if (vbuf->field == V4L2_FIELD_ANY)
+		vbuf->field = V4L2_FIELD_NONE;
+	if (vbuf->field != V4L2_FIELD_NONE)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int dma2d_buf_prepare(struct vb2_buffer *vb)
+{
+	struct dma2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct dma2d_frame *f = get_frame(ctx, vb->vb2_queue->type);
+
+	if (vb2_plane_size(vb, 0) < f->size)
+		return -EINVAL;
+
+	vb2_set_plane_payload(vb, 0, f->size);
+
+	return 0;
+}
+
+static void dma2d_buf_queue(struct vb2_buffer *vb)
+{
+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+	struct dma2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
+}
+
+static int dma2d_start_streaming(struct vb2_queue *q, unsigned int count)
+{
+	struct dma2d_ctx *ctx = vb2_get_drv_priv(q);
+	struct dma2d_frame *f = get_frame(ctx, q->type);
+
+	f->sequence = 0;
+	return 0;
+}
+
+static void dma2d_stop_streaming(struct vb2_queue *q)
+{
+	struct dma2d_ctx *ctx = vb2_get_drv_priv(q);
+	struct vb2_v4l2_buffer *vbuf;
+
+	for (;;) {
+		if (V4L2_TYPE_IS_OUTPUT(q->type))
+			vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+		else
+			vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+		if (!vbuf)
+			return;
+		v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
+	}
+}
+
+static const struct vb2_ops dma2d_qops = {
+	.queue_setup	= dma2d_queue_setup,
+	.buf_out_validate	 = dma2d_buf_out_validate,
+	.buf_prepare	= dma2d_buf_prepare,
+	.buf_queue	= dma2d_buf_queue,
+	.start_streaming = dma2d_start_streaming,
+	.stop_streaming  = dma2d_stop_streaming,
+	.wait_prepare	= vb2_ops_wait_prepare,
+	.wait_finish	= vb2_ops_wait_finish,
+};
+
+static int queue_init(void *priv, struct vb2_queue *src_vq,
+		      struct vb2_queue *dst_vq)
+{
+	struct dma2d_ctx *ctx = priv;
+	int ret;
+
+	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+	src_vq->drv_priv = ctx;
+	src_vq->ops = &dma2d_qops;
+	src_vq->mem_ops = &vb2_dma_contig_memops;
+	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+	src_vq->lock = &ctx->dev->mutex;
+	src_vq->dev = ctx->dev->v4l2_dev.dev;
+
+	ret = vb2_queue_init(src_vq);
+	if (ret)
+		return ret;
+
+	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+	dst_vq->drv_priv = ctx;
+	dst_vq->ops = &dma2d_qops;
+	dst_vq->mem_ops = &vb2_dma_contig_memops;
+	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+	dst_vq->lock = &ctx->dev->mutex;
+	dst_vq->dev = ctx->dev->v4l2_dev.dev;
+
+	return vb2_queue_init(dst_vq);
+}
+
+static int dma2d_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct dma2d_frame *frm;
+	struct dma2d_ctx *ctx = container_of(ctrl->handler, struct dma2d_ctx,
+								ctrl_handler);
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctx->dev->ctrl_lock, flags);
+	switch (ctrl->id) {
+	case V4L2_CID_COLORFX:
+		if (ctrl->val == V4L2_COLORFX_SET_RGB)
+			ctx->op_mode = DMA2D_MODE_R2M;
+		else if (ctrl->val == V4L2_COLORFX_NONE)
+			ctx->op_mode = DMA2D_MODE_M2M;
+		break;
+	case V4L2_CID_COLORFX_RGB:
+		frm = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
+		frm->a_rgb[2] = (ctrl->val >> 16) & 0xff;
+		frm->a_rgb[1] = (ctrl->val >> 8) & 0xff;
+		frm->a_rgb[0] = (ctrl->val >> 0) & 0xff;
+		break;
+	default:
+		v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
+		spin_unlock_irqrestore(&ctx->dev->ctrl_lock, flags);
+		return -EINVAL;
+	}
+	spin_unlock_irqrestore(&ctx->dev->ctrl_lock, flags);
+
+	return 0;
+}
+
+static const struct v4l2_ctrl_ops dma2d_ctrl_ops = {
+	.s_ctrl	= dma2d_s_ctrl,
+};
+
+static int dma2d_setup_ctrls(struct dma2d_ctx *ctx)
+{
+	struct v4l2_ctrl_handler *handler = &ctx->ctrl_handler;
+
+	v4l2_ctrl_handler_init(handler, 2);
+
+	v4l2_ctrl_new_std_menu(handler, &dma2d_ctrl_ops, V4L2_CID_COLORFX,
+			       V4L2_COLORFX_SET_RGB, ~0x10001,
+			       V4L2_COLORFX_NONE);
+
+	v4l2_ctrl_new_std(handler, &dma2d_ctrl_ops, V4L2_CID_COLORFX_RGB, 0,
+			  0xffffff, 1, 0);
+
+	return 0;
+}
+
+static int dma2d_open(struct file *file)
+{
+	struct dma2d_dev *dev = video_drvdata(file);
+	struct dma2d_ctx *ctx = NULL;
+	int ret = 0;
+
+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+	ctx->dev = dev;
+	/* Set default formats */
+	ctx->cap		= def_frame;
+	ctx->bg		= def_frame;
+	ctx->out	= def_frame;
+	ctx->op_mode	= DMA2D_MODE_M2M_FPC;
+	ctx->colorspace = V4L2_COLORSPACE_REC709;
+	if (mutex_lock_interruptible(&dev->mutex)) {
+		kfree(ctx);
+		return -ERESTARTSYS;
+	}
+
+	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
+	if (IS_ERR(ctx->fh.m2m_ctx)) {
+		ret = PTR_ERR(ctx->fh.m2m_ctx);
+		mutex_unlock(&dev->mutex);
+		kfree(ctx);
+		return ret;
+	}
+
+	v4l2_fh_init(&ctx->fh, video_devdata(file));
+	file->private_data = &ctx->fh;
+	v4l2_fh_add(&ctx->fh);
+
+	dma2d_setup_ctrls(ctx);
+
+	/* Write the default values to the ctx struct */
+	v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
+
+	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
+	mutex_unlock(&dev->mutex);
+
+	return 0;
+}
+
+static int dma2d_release(struct file *file)
+{
+	struct dma2d_dev *dev = video_drvdata(file);
+	struct dma2d_ctx *ctx = fh2ctx(file->private_data);
+
+	mutex_lock(&dev->mutex);
+	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
+	mutex_unlock(&dev->mutex);
+	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+	v4l2_fh_del(&ctx->fh);
+	v4l2_fh_exit(&ctx->fh);
+	kfree(ctx);
+
+	return 0;
+}
+
+static int vidioc_querycap(struct file *file, void *priv,
+			   struct v4l2_capability *cap)
+{
+	strscpy(cap->driver, DMA2D_NAME, sizeof(cap->driver));
+	strscpy(cap->card, DMA2D_NAME, sizeof(cap->card));
+	strscpy(cap->bus_info, BUS_INFO, sizeof(cap->bus_info));
+
+	return 0;
+}
+
+static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
+{
+	if (f->index >= NUM_FORMATS)
+		return -EINVAL;
+
+	f->pixelformat = formats[f->index].fourcc;
+	return 0;
+}
+
+static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
+{
+	struct dma2d_ctx *ctx = prv;
+	struct vb2_queue *vq;
+	struct dma2d_frame *frm;
+
+	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+	if (!vq)
+		return -EINVAL;
+
+	frm = get_frame(ctx, f->type);
+	f->fmt.pix.width		= frm->width;
+	f->fmt.pix.height		= frm->height;
+	f->fmt.pix.field		= V4L2_FIELD_NONE;
+	f->fmt.pix.pixelformat		= frm->fmt->fourcc;
+	f->fmt.pix.bytesperline		= (frm->width * frm->fmt->depth) >> 3;
+	f->fmt.pix.sizeimage		= frm->size;
+	f->fmt.pix.colorspace		= ctx->colorspace;
+	f->fmt.pix.xfer_func		= ctx->xfer_func;
+	f->fmt.pix.ycbcr_enc		= ctx->ycbcr_enc;
+	f->fmt.pix.quantization		= ctx->quant;
+
+	return 0;
+}
+
+static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
+{
+	struct dma2d_ctx *ctx = prv;
+	struct dma2d_dev *dev = ctx->dev;
+	struct dma2d_fmt *fmt;
+	enum v4l2_field *field;
+	u32 fourcc = f->fmt.pix.pixelformat;
+
+	fmt = find_fmt(fourcc);
+	if (!fmt) {
+		v4l2_warn(&dev->v4l2_dev,
+			  "Format not supported: %x%x%x%x, use the default.\n",
+			  (fourcc & 0xff),  (fourcc >>  8) & 0xff,
+			  (fourcc >> 16) & 0xff, (fourcc >> 24) & 0xff);
+		f->fmt.pix.pixelformat = formats[0].fourcc;
+		fmt = find_fmt(f->fmt.pix.pixelformat);
+	}
+
+	field = &f->fmt.pix.field;
+	if (*field == V4L2_FIELD_ANY)
+		*field = V4L2_FIELD_NONE;
+	else if (*field != V4L2_FIELD_NONE)
+		return -EINVAL;
+
+	if (f->fmt.pix.width > MAX_WIDTH)
+		f->fmt.pix.width = MAX_WIDTH;
+	if (f->fmt.pix.height > MAX_HEIGHT)
+		f->fmt.pix.height = MAX_HEIGHT;
+
+	if (f->fmt.pix.width < 1)
+		f->fmt.pix.width = 1;
+	if (f->fmt.pix.height < 1)
+		f->fmt.pix.height = 1;
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT && !f->fmt.pix.colorspace) {
+		f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		f->fmt.pix.colorspace	= ctx->colorspace;
+		f->fmt.pix.xfer_func = ctx->xfer_func;
+		f->fmt.pix.ycbcr_enc = ctx->ycbcr_enc;
+		f->fmt.pix.quantization = ctx->quant;
+	}
+	f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
+	f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
+
+	return 0;
+}
+
+static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
+{
+	struct dma2d_ctx *ctx = prv;
+	struct dma2d_dev *dev = ctx->dev;
+	struct vb2_queue *vq;
+	struct dma2d_frame *frm;
+	struct dma2d_fmt *fmt;
+	int ret = 0;
+
+	/* Adjust all values accordingly to the hardware capabilities
+	 * and chosen format.
+	 */
+	ret = vidioc_try_fmt(file, prv, f);
+	if (ret)
+		return ret;
+
+	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+	if (vb2_is_busy(vq)) {
+		v4l2_err(&dev->v4l2_dev, "queue (%d) bust\n", f->type);
+		return -EBUSY;
+	}
+
+	fmt = find_fmt(f->fmt.pix.pixelformat);
+	if (!fmt)
+		return -EINVAL;
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		ctx->colorspace = f->fmt.pix.colorspace;
+		ctx->xfer_func = f->fmt.pix.xfer_func;
+		ctx->ycbcr_enc = f->fmt.pix.ycbcr_enc;
+		ctx->quant = f->fmt.pix.quantization;
+	}
+
+	frm = get_frame(ctx, f->type);
+	frm->width = f->fmt.pix.width;
+	frm->height = f->fmt.pix.height;
+	frm->size = f->fmt.pix.sizeimage;
+	/* Reset crop settings */
+	frm->o_width = 0;
+	frm->o_height = 0;
+	frm->c_width = frm->width;
+	frm->c_height = frm->height;
+	frm->right = frm->width;
+	frm->bottom = frm->height;
+	frm->fmt = fmt;
+	frm->line_offset = 0;
+
+	return 0;
+}
+
+static void device_run(void *prv)
+{
+	struct dma2d_ctx *ctx = prv;
+	struct dma2d_dev *dev = ctx->dev;
+	struct dma2d_frame *frm_out, *frm_cap;
+	struct vb2_v4l2_buffer *src, *dst;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->ctrl_lock, flags);
+	dev->curr = ctx;
+
+	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+	dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
+	if (!dst || !src)
+		goto end;
+
+	frm_cap = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
+	frm_out = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
+	if (!frm_cap || !frm_out)
+		goto end;
+
+	src->sequence = frm_out->sequence++;
+	dst->sequence = frm_cap->sequence++;
+	v4l2_m2m_buf_copy_metadata(src, dst, true);
+
+	clk_enable(dev->gate);
+
+	dma2d_config_fg(dev, frm_out,
+			vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0));
+
+	/* TODO: add M2M_BLEND handler here */
+
+	if (ctx->op_mode != DMA2D_MODE_R2M) {
+		if (frm_out->fmt->fourcc == frm_cap->fmt->fourcc)
+			ctx->op_mode = DMA2D_MODE_M2M;
+		else
+			ctx->op_mode = DMA2D_MODE_M2M_FPC;
+	}
+
+	dma2d_config_out(dev, frm_cap,
+			 vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0));
+	dma2d_config_common(dev, ctx->op_mode, frm_cap->width, frm_cap->height);
+
+	dma2d_start(dev);
+end:
+	spin_unlock_irqrestore(&dev->ctrl_lock, flags);
+}
+
+static irqreturn_t dma2d_isr(int irq, void *prv)
+{
+	struct dma2d_dev *dev = prv;
+	struct dma2d_ctx *ctx = dev->curr;
+	struct vb2_v4l2_buffer *src, *dst;
+	u32 s = dma2d_get_int(dev);
+
+	dma2d_clear_int(dev);
+	if (s & ISR_TCIF || s == 0) {
+		clk_disable(dev->gate);
+
+		WARN_ON(!ctx);
+
+		src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+		dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+		WARN_ON(!dst);
+		WARN_ON(!src);
+
+		v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
+		v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
+		v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
+
+		dev->curr = NULL;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static const struct v4l2_file_operations dma2d_fops = {
+	.owner		= THIS_MODULE,
+	.open		= dma2d_open,
+	.release	= dma2d_release,
+	.poll		= v4l2_m2m_fop_poll,
+	.unlocked_ioctl	= video_ioctl2,
+	.mmap		= v4l2_m2m_fop_mmap,
+#ifndef CONFIG_MMU
+	.get_unmapped_area = v4l2_m2m_get_unmapped_area,
+#endif
+};
+
+static const struct v4l2_ioctl_ops dma2d_ioctl_ops = {
+	.vidioc_querycap	= vidioc_querycap,
+
+	.vidioc_enum_fmt_vid_cap	= vidioc_enum_fmt,
+	.vidioc_g_fmt_vid_cap		= vidioc_g_fmt,
+	.vidioc_try_fmt_vid_cap		= vidioc_try_fmt,
+	.vidioc_s_fmt_vid_cap		= vidioc_s_fmt,
+
+	.vidioc_enum_fmt_vid_out	= vidioc_enum_fmt,
+	.vidioc_g_fmt_vid_out		= vidioc_g_fmt,
+	.vidioc_try_fmt_vid_out		= vidioc_try_fmt,
+	.vidioc_s_fmt_vid_out		= vidioc_s_fmt,
+
+	.vidioc_reqbufs			= v4l2_m2m_ioctl_reqbufs,
+	.vidioc_querybuf		= v4l2_m2m_ioctl_querybuf,
+	.vidioc_qbuf			= v4l2_m2m_ioctl_qbuf,
+	.vidioc_dqbuf			= v4l2_m2m_ioctl_dqbuf,
+	.vidioc_prepare_buf		= v4l2_m2m_ioctl_prepare_buf,
+	.vidioc_create_bufs		= v4l2_m2m_ioctl_create_bufs,
+	.vidioc_expbuf			= v4l2_m2m_ioctl_expbuf,
+
+	.vidioc_streamon		= v4l2_m2m_ioctl_streamon,
+	.vidioc_streamoff		= v4l2_m2m_ioctl_streamoff,
+
+	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+};
+
+static const struct video_device dma2d_videodev = {
+	.name		= DMA2D_NAME,
+	.fops		= &dma2d_fops,
+	.ioctl_ops	= &dma2d_ioctl_ops,
+	.minor		= -1,
+	.release	= video_device_release,
+	.vfl_dir	= VFL_DIR_M2M,
+};
+
+static const struct v4l2_m2m_ops dma2d_m2m_ops = {
+	.device_run	= device_run,
+};
+
+static const struct of_device_id stm32_dma2d_match[];
+
+static int dma2d_probe(struct platform_device *pdev)
+{
+	struct dma2d_dev *dev;
+	struct video_device *vfd;
+	struct resource *res;
+	int ret = 0;
+
+	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	spin_lock_init(&dev->ctrl_lock);
+	mutex_init(&dev->mutex);
+	atomic_set(&dev->num_inst, 0);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	dev->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(dev->regs))
+		return PTR_ERR(dev->regs);
+
+	dev->gate = clk_get(&pdev->dev, "dma2d");
+	if (IS_ERR(dev->gate)) {
+		dev_err(&pdev->dev, "failed to get dma2d clock gate\n");
+		ret = -ENXIO;
+		return ret;
+	}
+
+	ret = clk_prepare(dev->gate);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to prepare dma2d clock gate\n");
+		goto put_clk_gate;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to find IRQ\n");
+		ret = -ENXIO;
+		goto unprep_clk_gate;
+	}
+
+	dev->irq = res->start;
+
+	ret = devm_request_irq(&pdev->dev, dev->irq, dma2d_isr,
+			       0, pdev->name, dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to install IRQ\n");
+		goto unprep_clk_gate;
+	}
+
+	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
+	if (ret)
+		goto unprep_clk_gate;
+
+	vfd = video_device_alloc();
+	if (!vfd) {
+		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
+		ret = -ENOMEM;
+		goto unreg_v4l2_dev;
+	}
+
+	*vfd = dma2d_videodev;
+	vfd->lock = &dev->mutex;
+	vfd->v4l2_dev = &dev->v4l2_dev;
+	vfd->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
+
+	platform_set_drvdata(pdev, dev);
+	dev->m2m_dev = v4l2_m2m_init(&dma2d_m2m_ops);
+	if (IS_ERR(dev->m2m_dev)) {
+		v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
+		ret = PTR_ERR(dev->m2m_dev);
+		goto rel_vdev;
+	}
+
+	ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
+	if (ret) {
+		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
+		goto free_m2m;
+	}
+
+	video_set_drvdata(vfd, dev);
+	dev->vfd = vfd;
+	v4l2_info(&dev->v4l2_dev, "device registered as /dev/video%d\n",
+		  vfd->num);
+	return 0;
+
+free_m2m:
+	v4l2_m2m_release(dev->m2m_dev);
+rel_vdev:
+	video_device_release(vfd);
+unreg_v4l2_dev:
+	v4l2_device_unregister(&dev->v4l2_dev);
+unprep_clk_gate:
+	clk_unprepare(dev->gate);
+put_clk_gate:
+	clk_put(dev->gate);
+
+	return ret;
+}
+
+static int dma2d_remove(struct platform_device *pdev)
+{
+	struct dma2d_dev *dev = platform_get_drvdata(pdev);
+
+	v4l2_info(&dev->v4l2_dev, "Removing " DMA2D_NAME);
+	v4l2_m2m_release(dev->m2m_dev);
+	video_unregister_device(dev->vfd);
+	v4l2_device_unregister(&dev->v4l2_dev);
+	vb2_dma_contig_clear_max_seg_size(&pdev->dev);
+	clk_unprepare(dev->gate);
+	clk_put(dev->gate);
+
+	return 0;
+}
+
+static const struct of_device_id stm32_dma2d_match[] = {
+	{
+		.compatible = "st,stm32-dma2d",
+		.data = NULL,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, stm32_dma2d_match);
+
+static struct platform_driver dma2d_pdrv = {
+	.probe		= dma2d_probe,
+	.remove		= dma2d_remove,
+	.driver		= {
+		.name = DMA2D_NAME,
+		.of_match_table = stm32_dma2d_match,
+	},
+};
+
+module_platform_driver(dma2d_pdrv);
+
+MODULE_AUTHOR("Dillon Min <dillon.minfei@gmail.com>");
+MODULE_DESCRIPTION("STM32 Chrom-Art Accelerator DMA2D driver");
+MODULE_LICENSE("GPL");