[PATCH] ARM: dts: ux500: Tag Janice display SPI correct
DORMANTno replies
From: Linus Walleij <hidden>
Date: 2021-09-14 16:32:20
Subsystem:
the rest · Maintainer:
Linus Torvalds
The s6e63m0 display used "type 3" SPI communication so flag the device as using negative clocking and polarity on the SPI bus. Signed-off-by: Linus Walleij <redacted> --- arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
index f14cf316a70a..825b62146134 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts@@ -266,6 +266,9 @@ panel@0 { pinctrl-names = "default"; pinctrl-0 = <&panel_default_mode>; spi-3wire; + /* TYPE 3: inverse clock polarity and phase */ + spi-cpha; + spi-cpol; port { panel_in: endpoint {
--
2.31.1
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