[PATCH v3 0/3] Allwinner R329 and D1 watchdog support

This series adds bindings and driver support for the R329 and D1
watchdogs. The R329 is fully backward-compatible, so no driver changes
are needed for it.

v3 of this series adds two new compatibles, as I discovered that the
immediate "soft reset" functionality was specific to the watchdog that
is part of the same block as the sun4i timer, and is not available in
the RISC-V or DSP watchdog instances.

My intention is to use the soft reset function as OpenSBI's system reset
backend, so it needs to know which watchdog instance has that feature.

Samuel Holland (3):
  dt-bindings: watchdog: sunxi: Add compatibles for R329
  dt-bindings: watchdog: sunxi: Add compatibles for D1
  watchdog: sunxi_wdt: Add support for D1

 .../watchdog/allwinner,sun4i-a10-wdt.yaml     | 48 ++++++++++++++++++-
 drivers/watchdog/sunxi_wdt.c                  | 20 +++++++-
 2 files changed, 66 insertions(+), 2 deletions(-)

-- 
2.31.1


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On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M)
divided by 750.  However, starting with R329, LOSC (OSC32k) is added as
an alternative clock source, with a bit to switch between them.

Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the
cycle counts to keep the timeouts independent of the clock source. This
keeps the programming interface backward-compatible.

Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs
at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The
first of these adds two more new registers, to allow software to
immediately assert the SoC reset signal. Add an additional "-reset"
suffix to signify the presence of this feature.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Changes v2 to v3:
 - Add else case
 - Add additional allwinner,sun50i-r329-wdt-reset compatible
Changes v1 to v2:
 - Switch clock-names from enum to const
 - Add descriptions to "clocks" items

 .../watchdog/allwinner,sun4i-a10-wdt.yaml     | 42 ++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
index 9aa3c313c49f..877f47759814 100644
--- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml

@@ -24,6 +24,8 @@ properties:
               - allwinner,sun50i-a100-wdt
               - allwinner,sun50i-h6-wdt
               - allwinner,sun50i-h616-wdt
+              - allwinner,sun50i-r329-wdt
+              - allwinner,sun50i-r329-wdt-reset
           - const: allwinner,sun6i-a31-wdt
       - items:
           - const: allwinner,suniv-f1c100s-wdt

@@ -33,7 +35,18 @@ properties:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: High-frequency oscillator input, divided internally
+      - description: Low-frequency oscillator input, only found on some variants
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+    items:
+      - const: hosc
+      - const: losc
 
   interrupts:
     maxItems: 1

@@ -44,6 +57,33 @@ required:
   - clocks
   - interrupts
 
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - allwinner,sun50i-r329-wdt
+          - allwinner,sun50i-r329-wdt-reset
+
+then:
+  properties:
+    clocks:
+      minItems: 2
+
+    clock-names:
+      minItems: 2
+
+  required:
+    - clock-names
+
+else:
+  properties:
+    clocks:
+      maxItems: 1
+
+    clock-names:
+      maxItems: 1
+
 unevaluatedProperties: false
 
 examples:

-- 
2.31.1


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D1 keeps the same register layout and clock sources as the R329, but it
adds a key field which must be set to update the watchdog's "CFG" and
"MODE" registers. Therefore it is not backward-compatible.

Similarly to the R329, the D1 has three watchdog instances, and only one
of them has the "soft reset" registers. So that instance needs an extra
compatible string.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Changes v2 to v3:
 - Add additional allwinner,sun20i-d1-wdt-reset compatible
Changes v1 to v2:
 - None

 .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml          | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
index 877f47759814..44cad9427ae6 100644
--- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml

@@ -30,6 +30,10 @@ properties:
       - items:
           - const: allwinner,suniv-f1c100s-wdt
           - const: allwinner,sun4i-a10-wdt
+      - const: allwinner,sun20i-d1-wdt
+      - items:
+          - const: allwinner,sun20i-d1-wdt-reset
+          - const: allwinner,sun20i-d1-wdt
 
   reg:
     maxItems: 1

@@ -62,6 +66,8 @@ if:
     compatible:
       contains:
         enum:
+          - allwinner,sun20i-d1-wdt
+          - allwinner,sun20i-d1-wdt-reset
           - allwinner,sun50i-r329-wdt
           - allwinner,sun50i-r329-wdt-reset
 

-- 
2.31.1


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D1 adds a key field to the "CFG" and "MODE" registers, that must be set
to change the other bits. Add logic to set the key when updating those
registers.

Acked-by: Maxime Ripard <redacted>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Changes v2 to v3:
 - None
Changes v1 to v2:
 - None

 drivers/watchdog/sunxi_wdt.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
index b50757882a98..6cf82922d3fb 100644
--- a/drivers/watchdog/sunxi_wdt.c
+++ b/drivers/watchdog/sunxi_wdt.c

@@ -48,6 +48,7 @@ struct sunxi_wdt_reg {
 	u8 wdt_timeout_shift;
 	u8 wdt_reset_mask;
 	u8 wdt_reset_val;
+	u32 wdt_key_val;
 };
 
 struct sunxi_wdt_dev {

@@ -91,12 +92,14 @@ static int sunxi_wdt_restart(struct watchdog_device *wdt_dev,
 	val = readl(wdt_base + regs->wdt_cfg);
 	val &= ~(regs->wdt_reset_mask);
 	val |= regs->wdt_reset_val;
+	val |= regs->wdt_key_val;
 	writel(val, wdt_base + regs->wdt_cfg);
 
 	/* Set lowest timeout and enable watchdog */
 	val = readl(wdt_base + regs->wdt_mode);
 	val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
 	val |= WDT_MODE_EN;
+	val |= regs->wdt_key_val;
 	writel(val, wdt_base + regs->wdt_mode);
 
 	/*

@@ -109,6 +112,7 @@ static int sunxi_wdt_restart(struct watchdog_device *wdt_dev,
 		mdelay(5);
 		val = readl(wdt_base + regs->wdt_mode);
 		val |= WDT_MODE_EN;
+		val |= regs->wdt_key_val;
 		writel(val, wdt_base + regs->wdt_mode);
 	}
 	return 0;

@@ -141,6 +145,7 @@ static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev,
 	reg = readl(wdt_base + regs->wdt_mode);
 	reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift);
 	reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift;
+	reg |= regs->wdt_key_val;
 	writel(reg, wdt_base + regs->wdt_mode);
 
 	sunxi_wdt_ping(wdt_dev);

@@ -154,7 +159,7 @@ static int sunxi_wdt_stop(struct watchdog_device *wdt_dev)
 	void __iomem *wdt_base = sunxi_wdt->wdt_base;
 	const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs;
 
-	writel(0, wdt_base + regs->wdt_mode);
+	writel(regs->wdt_key_val, wdt_base + regs->wdt_mode);
 
 	return 0;
 }

@@ -176,11 +181,13 @@ static int sunxi_wdt_start(struct watchdog_device *wdt_dev)
 	reg = readl(wdt_base + regs->wdt_cfg);
 	reg &= ~(regs->wdt_reset_mask);
 	reg |= regs->wdt_reset_val;
+	reg |= regs->wdt_key_val;
 	writel(reg, wdt_base + regs->wdt_cfg);
 
 	/* Enable watchdog */
 	reg = readl(wdt_base + regs->wdt_mode);
 	reg |= WDT_MODE_EN;
+	reg |= regs->wdt_key_val;
 	writel(reg, wdt_base + regs->wdt_mode);
 
 	return 0;

@@ -220,9 +227,20 @@ static const struct sunxi_wdt_reg sun6i_wdt_reg = {
 	.wdt_reset_val = 0x01,
 };
 
+static const struct sunxi_wdt_reg sun20i_wdt_reg = {
+	.wdt_ctrl = 0x10,
+	.wdt_cfg = 0x14,
+	.wdt_mode = 0x18,
+	.wdt_timeout_shift = 4,
+	.wdt_reset_mask = 0x03,
+	.wdt_reset_val = 0x01,
+	.wdt_key_val = 0x16aa0000,
+};
+
 static const struct of_device_id sunxi_wdt_dt_ids[] = {
 	{ .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
 	{ .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
+	{ .compatible = "allwinner,sun20i-d1-wdt", .data = &sun20i_wdt_reg },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);

-- 
2.31.1


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On Thu, Sep 02, 2021 at 05:57:48PM -0500, Samuel Holland wrote:

On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M)
divided by 750.  However, starting with R329, LOSC (OSC32k) is added as
an alternative clock source, with a bit to switch between them.

Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the
cycle counts to keep the timeouts independent of the clock source. This
keeps the programming interface backward-compatible.

Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs
at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The
first of these adds two more new registers, to allow software to
immediately assert the SoC reset signal. Add an additional "-reset"
suffix to signify the presence of this feature.

Signed-off-by: Samuel Holland <samuel@sholland.org>

Acked-by: Maxime Ripard <redacted>

Thanks!
Maxime

On Thu, Sep 02, 2021 at 05:57:49PM -0500, Samuel Holland wrote:

D1 keeps the same register layout and clock sources as the R329, but it
adds a key field which must be set to update the watchdog's "CFG" and
"MODE" registers. Therefore it is not backward-compatible.

Similarly to the R329, the D1 has three watchdog instances, and only one
of them has the "soft reset" registers. So that instance needs an extra
compatible string.

Signed-off-by: Samuel Holland <samuel@sholland.org>

Acked-by: Maxime Ripard <redacted>

Maxime

On Thu, 02 Sep 2021 17:57:48 -0500, Samuel Holland wrote:

On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M)
divided by 750.  However, starting with R329, LOSC (OSC32k) is added as
an alternative clock source, with a bit to switch between them.

Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the
cycle counts to keep the timeouts independent of the clock source. This
keeps the programming interface backward-compatible.

Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs
at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The
first of these adds two more new registers, to allow software to
immediately assert the SoC reset signal. Add an additional "-reset"
suffix to signify the presence of this feature.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Changes v2 to v3:
 - Add else case
 - Add additional allwinner,sun50i-r329-wdt-reset compatible
Changes v1 to v2:
 - Switch clock-names from enum to const
 - Add descriptions to "clocks" items

 .../watchdog/allwinner,sun4i-a10-wdt.yaml     | 42 ++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

Reviewed-by: Rob Herring <robh@kernel.org>

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

On Thu, Sep 02, 2021 at 05:57:48PM -0500, Samuel Holland wrote:

On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M)
divided by 750.  However, starting with R329, LOSC (OSC32k) is added as
an alternative clock source, with a bit to switch between them.

Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the
cycle counts to keep the timeouts independent of the clock source. This
keeps the programming interface backward-compatible.

Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs
at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The
first of these adds two more new registers, to allow software to
immediately assert the SoC reset signal. Add an additional "-reset"
suffix to signify the presence of this feature.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Maxime Ripard <redacted>
Reviewed-by: Rob Herring <robh@kernel.org>

Acked-by: Guenter Roeck <linux@roeck-us.net>

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

On Thu, Sep 02, 2021 at 05:57:49PM -0500, Samuel Holland wrote:

D1 keeps the same register layout and clock sources as the R329, but it
adds a key field which must be set to update the watchdog's "CFG" and
"MODE" registers. Therefore it is not backward-compatible.

Similarly to the R329, the D1 has three watchdog instances, and only one
of them has the "soft reset" registers. So that instance needs an extra
compatible string.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Maxime Ripard <redacted>

Acked-by: Guenter Roeck <linux@roeck-us.net>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

On Thu, 02 Sep 2021 17:57:49 -0500, Samuel Holland wrote:

D1 keeps the same register layout and clock sources as the R329, but it
adds a key field which must be set to update the watchdog's "CFG" and
"MODE" registers. Therefore it is not backward-compatible.

Similarly to the R329, the D1 has three watchdog instances, and only one
of them has the "soft reset" registers. So that instance needs an extra
compatible string.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
Changes v2 to v3:
 - Add additional allwinner,sun20i-d1-wdt-reset compatible
Changes v1 to v2:
 - None

 .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml          | 6 ++++++
 1 file changed, 6 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

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