[PATCH 1/2] arm64: dts: imx8mm-kontron-n801x-som: Fix the SPI chipselect polarity

Subsystems: arm/freescale imx / mxc arm architecture, the rest

STALE1776d

7 messages, 4 authors, 2021-09-22 · open the first message on its own page

[PATCH 1/2] arm64: dts: imx8mm-kontron-n801x-som: Fix the SPI chipselect polarity

From: Fabio Estevam <festevam@gmail.com>
Date: 2021-07-16 13:31:07

The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd for example:
    
[    4.854337] m25p80@0 enforce active low on chipselect handle
   
Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.
    
The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:
    
* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.
    
To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
index d0456daefda8..5a2805c51361 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
@@ -63,7 +63,7 @@ opp-750M {
 &ecspi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1>;
-	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	spi-flash@0 {
-- 
2.25.1


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[PATCH 2/2] arm64: dts: imx8mm-venice: Fix the SPI chipselect polarity

From: Fabio Estevam <festevam@gmail.com>
Date: 2021-07-16 13:31:06

The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd for example:
    
[    4.854337] m25p80@0 enforce active low on chipselect handle
   
Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.
    
The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:
    
* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.
    
To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
index 905b68a3daa5..138bb8c9bf56 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
@@ -57,7 +57,7 @@ reg_usb_otg1_vbus: regulator-usb-otg1 {
 &ecspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_spi2>;
-	cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
index b7c91bdc21dd..27afa46a253a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
@@ -76,7 +76,7 @@ reg_usb_otg2_vbus: regulator-usb-otg2 {
 &ecspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_spi2>;
-	cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
index d2ffd62a3bd4..a59e849c7be2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
@@ -96,7 +96,7 @@ reg_wifi_en: regulator-wifi-en {
 &ecspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_spi2>;
-	cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
-- 
2.25.1


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Re: [PATCH 2/2] arm64: dts: imx8mm-venice: Fix the SPI chipselect polarity

From: Tim Harvey <tharvey@gateworks.com>
Date: 2021-07-16 14:54:14

On Fri, Jul 16, 2021 at 6:29 AM Fabio Estevam [off-list ref] wrote:
quoted hunk
The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd for example:

[    4.854337] m25p80@0 enforce active low on chipselect handle

Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.

The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:

* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.

To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +-
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
index 905b68a3daa5..138bb8c9bf56 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
@@ -57,7 +57,7 @@ reg_usb_otg1_vbus: regulator-usb-otg1 {
 &ecspi2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_spi2>;
-       cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
        status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
index b7c91bdc21dd..27afa46a253a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
@@ -76,7 +76,7 @@ reg_usb_otg2_vbus: regulator-usb-otg2 {
 &ecspi2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_spi2>;
-       cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
        status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
index d2ffd62a3bd4..a59e849c7be2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
@@ -96,7 +96,7 @@ reg_wifi_en: regulator-wifi-en {
 &ecspi2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_spi2>;
-       cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
        status = "okay";
 };

--
2.25.1
Fabio,

Thanks for finding this and submitting the patch!

Reviewed-By: Tim Harvey <tharvey@gateworks.com>

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Re: [PATCH 1/2] arm64: dts: imx8mm-kontron-n801x-som: Fix the SPI chipselect polarity

From: Frieder Schrempf <hidden>
Date: 2021-07-19 11:04:39

On 16.07.21 15:28, Fabio Estevam wrote:
The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd for example:
    
[    4.854337] m25p80@0 enforce active low on chipselect handle
   
Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.
    
The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:
    
* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.
    
To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Thanks for the fix!

Reviewed-by: Frieder Schrempf <redacted>

Shouldn't we consider to add the following tag, as this is clearly a bug in the original implementation of the DTS and the commit that uncovers this is already in multiple stable releases?

Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards")
quoted hunk
---
 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
index d0456daefda8..5a2805c51361 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
@@ -63,7 +63,7 @@ opp-750M {
 &ecspi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1>;
-	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	spi-flash@0 {
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Re: [PATCH 1/2] arm64: dts: imx8mm-kontron-n801x-som: Fix the SPI chipselect polarity

From: Fabio Estevam <festevam@gmail.com>
Date: 2021-08-14 13:27:32

Hi Shawn,

On Mon, Jul 19, 2021 at 7:55 AM Frieder Schrempf
[off-list ref] wrote:
Thanks for the fix!

Reviewed-by: Frieder Schrempf <redacted>

Shouldn't we consider to add the following tag, as this is clearly a bug in the original implementation of the DTS and the commit that uncovers this is already in multiple stable releases?

Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards")
Can you add the Fixes tag, or should I resend it?

Thanks

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Re: [PATCH 1/2] arm64: dts: imx8mm-kontron-n801x-som: Fix the SPI chipselect polarity

From: Shawn Guo <shawnguo@kernel.org>
Date: 2021-09-22 01:25:30

On Sat, Aug 14, 2021 at 10:25:24AM -0300, Fabio Estevam wrote:
Hi Shawn,

On Mon, Jul 19, 2021 at 7:55 AM Frieder Schrempf
[off-list ref] wrote:
quoted
Thanks for the fix!

Reviewed-by: Frieder Schrempf <redacted>

Shouldn't we consider to add the following tag, as this is clearly a bug in the original implementation of the DTS and the commit that uncovers this is already in multiple stable releases?

Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards")
Can you add the Fixes tag, or should I resend it?
Resend, please.

If this one needs a Fixes tag, the other one does too, right?

Shawn

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Re: [PATCH 1/2] arm64: dts: imx8mm-kontron-n801x-som: Fix the SPI chipselect polarity

From: Shawn Guo <shawnguo@kernel.org>
Date: 2021-09-22 03:03:30

On Fri, Jul 16, 2021 at 10:28:44AM -0300, Fabio Estevam wrote:
The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd for example:
    
[    4.854337] m25p80@0 enforce active low on chipselect handle
   
Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.
    
The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:
    
* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.
    
To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Applied both, thanks!

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