From: Peter Geis <hidden> Date: 2021-07-28 18:01:02
Good Morning,
This series aims to fix some early issues with the rk356x and enable
nodes that are currently supported by the available drivers.
1. fixes the mbi-alias, which points to the wrong location
2. fixes the rockchip clk-pll to work without a grf node
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adjusts the gpll and ppll clocks to better support hardware
7. enables the gmac1 on the Quartz64
8. adds thermal support to the Quartz64
Changelog:
v2:
Drop "dt-bindings: gpio: rockchip,gpio-bank: increase max clocks"
Drop "arm64: dts: rockchip: add missing rk3568 cru phandles"
Add clk-pll fix patch as suggested by Heiko
Move ethernet alias to Quartz64 board as suggested by Heiko
Adjust tsadc pinctrl as suggested by Heiko and Johan
Move tsadc mode and polarity to Quartz64 board
Peter Geis (8):
arm64: dts: rockchip: fix rk3568 mbi-alias
clk: rockchip: fix clk-pll rk356x early pll init
arm64: dts: rockchip: add rk356x gpio debounce clocks
arm64: dts: rockchip: add rk356x gmac1 node
arm64: dts: rockchip: add rk3568 tsadc nodes
arm64: dts: rockchip: adjust rk3568 pll clocks
arm64: dts: rockchip: enable gmac node on quartz64-a
arm64: dts: rockchip: add thermal support to Quartz64 Model A
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 71 ++++++++++
.../boot/dts/rockchip/rk3568-pinctrl.dtsi | 7 +
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 131 +++++++++++++++++-
drivers/clk/rockchip/clk-pll.c | 2 +-
4 files changed, 204 insertions(+), 7 deletions(-)
--
2.25.1
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From: Peter Geis <hidden> Date: 2021-07-28 18:01:01
The mbi-alias incorrectly points to 0xfd100000 when it should point to
0xfd410000.
This fixes MSIs on rk3568.
Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568
SoC")
Signed-off-by: Peter Geis <redacted>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Peter Geis <hidden> Date: 2021-07-28 18:01:05
The rk356x needs to reclock certain plls at boot. If the grf phandles
are not linked in the cru and pmucru nodes, it is unable to apply any
assigned-clock-rates at boot.
Fix this by removing the check for the grf for selecting the utilized
operations.
"The rk3568 reuses the pll_rk3328-type which in turn is a modified
pll_rk3036 and uses their ops. Which in turn means the pll shouldn't
access the GRF at all, as it uses the pll's own register to check the
locked state."
Suggested-by: Heiko Stuebner <heiko@sntech.de>
Link:
https://lore.kernel.org/linux-devicetree/20210728135534.703028-7-pgwipeout@gmail.com/
Fixes: c9c3c6eecc55 ("clk: rockchip: simplify GRF handling in pll
clocks")
Signed-off-by: Peter Geis <redacted>
---
drivers/clk/rockchip/clk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Peter Geis <hidden> Date: 2021-07-28 18:01:09
The rk356x added a debounce clock to the gpio devices. This clock is
necessary for the new v2 gpio driver to bind.
Add the clocks to the rk356x device tree.
Signed-off-by: Peter Geis <redacted>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
From: Peter Geis <hidden> Date: 2021-07-28 18:01:09
Add the gmac1 controller to the rk356x device tree.
This is the controller common to both the rk3568 and rk3566.
Signed-off-by: Peter Geis <redacted>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
1 file changed, 47 insertions(+)
From: Peter Geis <hidden> Date: 2021-07-28 18:01:11
Add the thermal and tsadc nodes to the rk3568 device tree.
There are two sensors, one for the cpu, one for the gpu.
Signed-off-by: Peter Geis <redacted>
---
.../boot/dts/rockchip/rk3568-pinctrl.dtsi | 7 ++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++
2 files changed, 77 insertions(+)
From: Peter Geis <hidden> Date: 2021-07-28 18:01:16
Enable the gmac controller on the Pine64 Quartz64 Model A.
Signed-off-by: Peter Geis <redacted>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
@@ -116,6 +124,29 @@ &cpu3 {cpu-supply=<&vdd_cpu>;};+&gmac1{+assigned-clocks=<&cruSCLK_GMAC1_RX_TX>,<&cruSCLK_GMAC1_RGMII_SPEED>,<&cruSCLK_GMAC1>;+assigned-clock-parents=<&cruSCLK_GMAC1_RGMII_SPEED>,<&cruSCLK_GMAC1>,<&gmac1_clkin>;+clock_in_out="input";+phy-supply=<&vcc_3v3>;+phy-mode="rgmii";+pinctrl-names="default";+pinctrl-0=<&gmac1m0_miim+&gmac1m0_tx_bus2+&gmac1m0_rx_bus2+&gmac1m0_rgmii_clk+&gmac1m0_clkinout+&gmac1m0_rgmii_bus>;+snps,reset-gpio=<&gpio0RK_PC3GPIO_ACTIVE_LOW>;+snps,reset-active-low;+/* Reset time is 20ms, 100ms for rtl8211f */+snps,reset-delays-us=<020000100000>;+tx_delay=<0x30>;+rx_delay=<0x10>;+phy-handle=<&rgmii_phy1>;+status="okay";+};+&i2c0{status="okay";
From: Peter Geis <hidden> Date: 2021-07-28 18:01:21
The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
These are set incorrectly by the bootloader, so fix them here.
Signed-off-by: Peter Geis <redacted>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
1 file changed, 2 insertions(+)
From: Peter Geis <hidden> Date: 2021-07-28 18:01:22
Add the thermal nodes for the Quartz64 Model A.
The Model A supports a single speed gpio fan.
Signed-off-by: Peter Geis <redacted>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
Hi Peter, Kever,
Am Mittwoch, 28. Juli 2021, 20:00:31 CEST schrieb Peter Geis:
quoted hunk
Add the thermal and tsadc nodes to the rk3568 device tree.
There are two sensors, one for the cpu, one for the gpu.
Signed-off-by: Peter Geis <redacted>
---
.../boot/dts/rockchip/rk3568-pinctrl.dtsi | 7 ++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++
2 files changed, 77 insertions(+)
The rk3568-pinctrl.dtsi is autogenerated on Rockchip's side and I don't
want to break that unnecessarily ;-) .
So the question below is more for Kever and Liang:
The tsadc on most mainline Rockchip socs uses the additional init-pinctrl
to set the pin to gpio mode before the tsadc probes and only to the shutdown
function after the tsadc has probed sucessfully. This prevents the
shutdown firing before the tsadc actually attached to the pin function.
Is it possible to fit the above addition pin setting in the database you
have as base for the autogeneration?
Thanks
Heiko
On Wed, 28 Jul 2021 14:00:26 -0400, Peter Geis wrote:
Good Morning,
This series aims to fix some early issues with the rk356x and enable
nodes that are currently supported by the available drivers.
1. fixes the mbi-alias, which points to the wrong location
2. fixes the rockchip clk-pll to work without a grf node
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adjusts the gpll and ppll clocks to better support hardware
7. enables the gmac1 on the Quartz64
8. adds thermal support to the Quartz64
[...]
Applied the easy ones for now, thanks!
[1/8] arm64: dts: rockchip: fix rk3568 mbi-alias
commit: 0ecf7b9137e05e2ade45b0555b00248cc0b7ac69
-> just put that in for 5.15, as the rk3568 on 5.14 is
still largely a wip
[2/8] clk: rockchip: fix clk-pll rk356x early pll init
commit: 6fffe52fb336ec2063270a7305652a93ea677ca1
-> I've adapted the commit message here
[4/8] arm64: dts: rockchip: add rk356x gmac1 node
commit: 6cdca5eb64c6eff6d552b475b6dc9182d84f2a31
-> did a bit of sorting here
[6/8] arm64: dts: rockchip: adjust rk3568 pll clocks
commit: 66a6450203e2e9bcaf6cb5938e7a9a159234722a
-> adapted commit message with your reply from v1
[7/8] arm64: dts: rockchip: enable gmac node on quartz64-a
commit: 797fc427ffb9a746d985c5f31e9c14defc1d1187
Best regards,
--
Heiko Stuebner [off-list ref]
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On Wed, 28 Jul 2021 14:00:26 -0400, Peter Geis wrote:
Good Morning,
This series aims to fix some early issues with the rk356x and enable
nodes that are currently supported by the available drivers.
1. fixes the mbi-alias, which points to the wrong location
2. fixes the rockchip clk-pll to work without a grf node
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adjusts the gpll and ppll clocks to better support hardware
7. enables the gmac1 on the Quartz64
8. adds thermal support to the Quartz64
[...]
On Wed, 28 Jul 2021 14:00:26 -0400, Peter Geis wrote:
Good Morning,
This series aims to fix some early issues with the rk356x and enable
nodes that are currently supported by the available drivers.
1. fixes the mbi-alias, which points to the wrong location
2. fixes the rockchip clk-pll to work without a grf node
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adjusts the gpll and ppll clocks to better support hardware
7. enables the gmac1 on the Quartz64
8. adds thermal support to the Quartz64
[...]
Applied, thanks!
[5/8] arm64: dts: rockchip: add rk3568 tsadc nodes
commit: 1a9563ba0a59b221156d80a3a77a43fdd144576c
[I've moved the tsadc-pin pin setting to the second pinctrl
block meant to hand-crafted pin settings in rk3568-pinctrl.dtsi]
[8/8] arm64: dts: rockchip: add thermal support to Quartz64 Model A
commit: d0e2e61b3cbaab474e2093ceb2073c4441bd36f8
Looks like we're all done with that series now.
Best regards,
--
Heiko Stuebner [off-list ref]
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