From: Steven Lee <hidden> Date: 2021-07-12 10:03:30
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.
For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins by dts ngpios property.
- Pair input/output GPIOs instead of using 0 as GPIO input pin base and
MAX_NR_HW_SGPIO as GPIO output pin base.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
irq_chip data.
- Replace all of_*() APIs with device_*().
Changes from v5:
* Squash v5 patch-05 and patch-06 to one patch.
* Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
input/output pin base are determined by ngpios.
For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
pin order is as follows:
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
With the new design, pin order is changed as follows:
Input:
0 2 4 6 ... 18(ngpios * 2 - 2)
Output:
1 3 5 7 ... 19(ngpios * 2 - 1)
* Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
ast2600-sgpiom.
* Fix coding style issues.
Changes from v4:
* Remove ngpios from dtsi
* Add ast2400 and ast2500 platform data.
* Remove unused macros.
* Add ngpios check in a separate patch.
* Fix coding style issues.
Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().
Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
max_ngpios.
* Split sgpio driver patch to 3 patches
Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.
Please help to review.
Thanks,
Steven
Steven Lee (9):
dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
dt-bindings: aspeed-sgpio: Add ast2600 sgpio
ARM: dts: aspeed-g6: Add SGPIO node.
ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
gpio: gpio-aspeed-sgpio: Add set_config function
gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
gpio: gpio-aspeed-sgpio: Use generic device property APIs
gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
.../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
5 files changed, 215 insertions(+), 115 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
--
2.17.1
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@@ -0,0 +1,75 @@+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)+%YAML1.2+---+$id:http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:Aspeed SGPIO controller++maintainers:+-Andrew Jeffery <andrew@aj.id.au>++description:+This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full+featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to+support the following options+-Support interrupt option for each input port and various interrupt+sensitivity option (level-high, level-low, edge-high, edge-low)+-Support reset tolerance option for each output port+-Directly connected to APB bus and its shift clock is from APB bus clock+divided by a programmable value.+-Co-work with external signal-chained TTL components (74LV165/74LV595)++properties:+compatible:+enum:+-aspeed,ast2400-sgpio+-aspeed,ast2500-sgpio++reg:+maxItems:1++gpio-controller:true++'#gpio-cells':+const:2++interrupts:+maxItems:1++interrupt-controller:true++clocks:+maxItems:1++ngpios:true++bus-frequency:true++required:+-compatible+-reg+-gpio-controller+-'#gpio-cells'+-interrupts+-interrupt-controller+-ngpios+-clocks+-bus-frequency++additionalProperties:false++examples:+-|+#include <dt-bindings/clock/aspeed-clock.h>+sgpio:sgpio@1e780200 {+#gpio-cells = <2>;+compatible = "aspeed,ast2500-sgpio";+gpio-controller;+interrupts = <40>;+reg = <0x1e780200 0x0100>;+clocks = <&syscon ASPEED_CLK_APB>;+interrupt-controller;+ngpios = <80>;+bus-frequency = <12000000>;+};
@@ -1,46 +0,0 @@-Aspeed SGPIO controller Device Tree Bindings-----------------------------------------------This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full-featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to-support the following options:-- Support interrupt option for each input port and various interrupt- sensitivity option (level-high, level-low, edge-high, edge-low)-- Support reset tolerance option for each output port-- Directly connected to APB bus and its shift clock is from APB bus clock- divided by a programmable value.-- Co-work with external signal-chained TTL components (74LV165/74LV595)--Required properties:--- compatible : Should be one of- "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"-- #gpio-cells : Should be 2, see gpio.txt-- reg : Address and length of the register set for the device-- gpio-controller : Marks the device node as a GPIO controller-- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt-- interrupt-controller : Mark the GPIO controller as an interrupt-controller-- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose- 2 software GPIOs per hardware GPIO: one for hardware input, one for hardware- output. Up to 80 pins, must be a multiple of 8.-- clocks : A phandle to the APB clock for SGPM clock division-- bus-frequency : SGPM CLK frequency--The sgpio and interrupt properties are further described in their respective-bindings documentation:--- Documentation/devicetree/bindings/gpio/gpio.txt-- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt-- Example:- sgpio: sgpio@1e780200 {- #gpio-cells = <2>;- compatible = "aspeed,ast2500-sgpio";- gpio-controller;- interrupts = <40>;- reg = <0x1e780200 0x0100>;- clocks = <&syscon ASPEED_CLK_APB>;- interrupt-controller;- ngpios = <8>;- bus-frequency = <12000000>;- };
--
2.17.1
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From: Steven Lee <hidden> Date: 2021-07-12 10:03:39
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins. Add ast2600-sgpiom compatibles and update descriptions to
introduce the max number of available gpio pins that AST2600 supported.
Signed-off-by: Steven Lee <redacted>
---
Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
@@ -10,9 +10,10 @@ maintainers:-Andrew Jeffery <andrew@aj.id.au>description:-This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full-featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to-support the following options+This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,+AST2600 have two sgpio master one with 128 pins another one with 80 pins,+AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial+GPIO pins can be programmed to support the following options-Support interrupt option for each input port and various interruptsensitivity option (level-high, level-low, edge-high, edge-low)-Support reset tolerance option for each output port
From: Steven Lee <hidden> Date: 2021-07-12 10:03:53
AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.
Signed-off-by: Steven Lee <redacted>
---
arch/arm/boot/dts/aspeed-g6.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
From: Steven Lee <hidden> Date: 2021-07-12 10:04:00
Remove ngpios property from sgpio node as it should be defined in the
platform dts.
Signed-off-by: Steven Lee <redacted>
Reviewed-by: Andrew Jeffery <redacted>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
1 file changed, 1 deletion(-)
From: Steven Lee <hidden> Date: 2021-07-12 10:04:07
The maximum number of gpio pins of SoC is hardcoded as 80 and the gpio pin
count mask for GPIO Configuration register is hardcode as GENMASK(9,6).
However, AST2600 has 2 sgpio master interfaces, one of them supports up
to 128 gpio pins and pin count mask of GPIO Configuration Register is 5
bits.
The patch adds ast2600 compatibles, removes MAX_NR_HW_SGPIO and
corresponding design to make the gpio input/output pin base are determined
by ngpios.
The patch also removed hardcoded pin mask and adds ast2400, ast2500,
ast2600 platform data that include gpio pin count mask for GPIO
Configuration Register.
The original pin order is as follows:
(suppose MAX_NR_HW_SGPIO is 80 and ngpios is 10 as well)
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
The new pin order is as follows:
Input:
0 2 4 6 ... 18
Output:
1 3 5 7 ... 19
SGPIO pin id and input/output pin mapping is as follows:
SGPIO0(0,1), SGPIO1(2,3), ..., SGPIO79(158,159)
For example:
Access SGPIO5(10,11)
Get SGPIO pin 5 (suppose sgpio chip id is 2)
gpioget 2 10
Set SGPIO pin 5 (suppose sgpio chip id is 2)
gpioset 2 11=1
gpioset 2 11=0
Signed-off-by: Steven Lee <redacted>
---
drivers/gpio/gpio-aspeed-sgpio.c | 101 ++++++++++++++-----------------
1 file changed, 47 insertions(+), 54 deletions(-)
@@ -138,39 +135,25 @@ static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)staticintaspeed_sgpio_init_valid_mask(structgpio_chip*gc,unsignedlong*valid_mask,unsignedintngpios){-structaspeed_sgpio*sgpio=gpiochip_get_data(gc);-intn=sgpio->n_sgpio;-intc=SGPIO_OUTPUT_OFFSET-n;--WARN_ON(ngpios<MAX_NR_HW_SGPIO*2);--/* input GPIOs in the lower range */-bitmap_set(valid_mask,0,n);-bitmap_clear(valid_mask,n,c);--/* output GPIOS above SGPIO_OUTPUT_OFFSET */-bitmap_set(valid_mask,SGPIO_OUTPUT_OFFSET,n);-bitmap_clear(valid_mask,SGPIO_OUTPUT_OFFSET+n,c);-+bitmap_set(valid_mask,0,ngpios);return0;}staticvoidaspeed_sgpio_irq_init_valid_mask(structgpio_chip*gc,unsignedlong*valid_mask,unsignedintngpios){-structaspeed_sgpio*sgpio=gpiochip_get_data(gc);-intn=sgpio->n_sgpio;+unsignedinti;-WARN_ON(ngpios<MAX_NR_HW_SGPIO*2);--/* input GPIOs in the lower range */-bitmap_set(valid_mask,0,n);-bitmap_clear(valid_mask,n,ngpios-n);+/* input GPIOs are even bits */+for(i=0;i<ngpios;i++){+if(i%2)+clear_bit(i,valid_mask);+}}staticboolaspeed_sgpio_is_input(unsignedintoffset){-returnoffset<SGPIO_OUTPUT_OFFSET;+return!(offset%2);}staticintaspeed_sgpio_get(structgpio_chip*gc,unsignedintoffset)
@@ -466,9 +449,18 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,return0;}+staticconststructaspeed_sgpio_pdataast2400_sgpio_pdata={+.pin_mask=GENMASK(9,6),+};++staticconststructaspeed_sgpio_pdataast2600_sgpiom_pdata={+.pin_mask=GENMASK(10,6),+};+staticconststructof_device_idaspeed_sgpio_of_table[]={-{.compatible="aspeed,ast2400-sgpio"},-{.compatible="aspeed,ast2500-sgpio"},+{.compatible="aspeed,ast2400-sgpio",.data=&ast2400_sgpio_pdata,},+{.compatible="aspeed,ast2500-sgpio",.data=&ast2400_sgpio_pdata,},+{.compatible="aspeed,ast2600-sgpiom",.data=&ast2600_sgpiom_pdata,},{}};
@@ -489,16 +482,17 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)if(IS_ERR(gpio->base))returnPTR_ERR(gpio->base);+pdata=device_get_match_data(&pdev->dev);+if(!pdata)+return-EINVAL;++pin_mask=pdata->pin_mask;+rc=of_property_read_u32(pdev->dev.of_node,"ngpios",&nr_gpios);if(rc<0){dev_err(&pdev->dev,"Could not read ngpios property\n");return-EINVAL;-}elseif(nr_gpios>MAX_NR_HW_SGPIO){-dev_err(&pdev->dev,"Number of GPIOs exceeds the maximum of %d: %d\n",-MAX_NR_HW_SGPIO,nr_gpios);-return-EINVAL;}-gpio->n_sgpio=nr_gpios;rc=of_property_read_u32(pdev->dev.of_node,"bus-frequency",&sgpio_freq);if(rc<0){
@@ -531,15 +525,14 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)if(sgpio_clk_div>(1<<16)-1)return-EINVAL;-iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK,sgpio_clk_div)|-FIELD_PREP(ASPEED_SGPIO_PINS_MASK,(nr_gpios/8))|-ASPEED_SGPIO_ENABLE,-gpio->base+ASPEED_SGPIO_CTRL);+gpio_cnt_regval=((nr_gpios/8)<<ASPEED_SGPIO_PINS_SHIFT)&pin_mask;+iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK,sgpio_clk_div)|gpio_cnt_regval|+ASPEED_SGPIO_ENABLE,gpio->base+ASPEED_SGPIO_CTRL);spin_lock_init(&gpio->lock);gpio->chip.parent=&pdev->dev;-gpio->chip.ngpio=MAX_NR_HW_SGPIO*2;+gpio->chip.ngpio=nr_gpios*2;gpio->chip.init_valid_mask=aspeed_sgpio_init_valid_mask;gpio->chip.direction_input=aspeed_sgpio_dir_in;gpio->chip.direction_output=aspeed_sgpio_dir_out;
--
2.17.1
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From: Steven Lee <hidden> Date: 2021-07-12 10:04:20
The current design initializes irq->chip from a global irqchip struct,
which causes multiple sgpio devices use the same irq_chip.
The patch moves irq_chip to aspeed_sgpio struct for initializing
irq_chip from their private gpio struct.
Signed-off-by: Steven Lee <redacted>
Reviewed-by: Andrew Jeffery <redacted>
---
drivers/gpio/gpio-aspeed-sgpio.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
From: Steven Lee <hidden> Date: 2021-07-12 10:04:23
Replace all of_property_read_u32() with device_property_read_u32().
Signed-off-by: Steven Lee <redacted>
Acked-by: Andrew Jeffery <redacted>
---
drivers/gpio/gpio-aspeed-sgpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
From: Steven Lee <hidden> Date: 2021-07-12 10:04:28
Add an else-if condition in the probe function to check whether ngpios is
multiple of 8.
Per AST datasheet, numbers of available serial GPIO pins in Serial GPIO
Configuration Register must be n bytes. For instance, if n = 1, it means
AST SoC supports 8 GPIO pins.
Signed-off-by: Steven Lee <redacted>
Reviewed-by: Andrew Jeffery <redacted>
---
drivers/gpio/gpio-aspeed-sgpio.c | 4 ++++
1 file changed, 4 insertions(+)
@@ -537,6 +537,10 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)if(rc<0){dev_err(&pdev->dev,"Could not read ngpios property\n");return-EINVAL;+}elseif(nr_gpios%8){+dev_err(&pdev->dev,"Number of GPIOs not multiple of 8: %d\n",+nr_gpios);+return-EINVAL;}rc=device_property_read_u32(&pdev->dev,"bus-frequency",&sgpio_freq);
--
2.17.1
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From: Rob Herring <robh@kernel.org> Date: 2021-07-13 22:44:16
On Mon, 12 Jul 2021 18:03:09 +0800, Steven Lee wrote:
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins. Add ast2600-sgpiom compatibles and update descriptions to
introduce the max number of available gpio pins that AST2600 supported.
Signed-off-by: Steven Lee <redacted>
---
Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee [off-list ref] wrote:
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.
For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins by dts ngpios property.
- Pair input/output GPIOs instead of using 0 as GPIO input pin base and
MAX_NR_HW_SGPIO as GPIO output pin base.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
irq_chip data.
- Replace all of_*() APIs with device_*().
Changes from v5:
* Squash v5 patch-05 and patch-06 to one patch.
* Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
input/output pin base are determined by ngpios.
For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
pin order is as follows:
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
With the new design, pin order is changed as follows:
Input:
0 2 4 6 ... 18(ngpios * 2 - 2)
Output:
1 3 5 7 ... 19(ngpios * 2 - 1)
* Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
ast2600-sgpiom.
* Fix coding style issues.
Changes from v4:
* Remove ngpios from dtsi
* Add ast2400 and ast2500 platform data.
* Remove unused macros.
* Add ngpios check in a separate patch.
* Fix coding style issues.
Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().
Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
max_ngpios.
* Split sgpio driver patch to 3 patches
Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.
Please help to review.
Thanks,
Steven
Steven Lee (9):
dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
dt-bindings: aspeed-sgpio: Add ast2600 sgpio
ARM: dts: aspeed-g6: Add SGPIO node.
ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
gpio: gpio-aspeed-sgpio: Add set_config function
gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
gpio: gpio-aspeed-sgpio: Use generic device property APIs
gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
.../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
5 files changed, 215 insertions(+), 115 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
--
2.17.1
The series looks good to me. Can the DTS and GPIO patches go into
v5.15 separately?
Bart
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From: Steven Lee <hidden> Date: 2021-07-23 03:16:30
The 07/21/2021 21:27, Bartosz Golaszewski wrote:
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee [off-list ref] wrote:
quoted
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.
For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins by dts ngpios property.
- Pair input/output GPIOs instead of using 0 as GPIO input pin base and
MAX_NR_HW_SGPIO as GPIO output pin base.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
irq_chip data.
- Replace all of_*() APIs with device_*().
Changes from v5:
* Squash v5 patch-05 and patch-06 to one patch.
* Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
input/output pin base are determined by ngpios.
For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
pin order is as follows:
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
With the new design, pin order is changed as follows:
Input:
0 2 4 6 ... 18(ngpios * 2 - 2)
Output:
1 3 5 7 ... 19(ngpios * 2 - 1)
* Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
ast2600-sgpiom.
* Fix coding style issues.
Changes from v4:
* Remove ngpios from dtsi
* Add ast2400 and ast2500 platform data.
* Remove unused macros.
* Add ngpios check in a separate patch.
* Fix coding style issues.
Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().
Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
max_ngpios.
* Split sgpio driver patch to 3 patches
Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.
Please help to review.
Thanks,
Steven
Steven Lee (9):
dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
dt-bindings: aspeed-sgpio: Add ast2600 sgpio
ARM: dts: aspeed-g6: Add SGPIO node.
ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
gpio: gpio-aspeed-sgpio: Add set_config function
gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
gpio: gpio-aspeed-sgpio: Use generic device property APIs
gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
.../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
5 files changed, 215 insertions(+), 115 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
--
2.17.1
The series looks good to me. Can the DTS and GPIO patches go into
v5.15 separately?
Hi Bart,
Thanks for the review.
Shall we do anything to make the patches go into v5.15 or wait for picking-up?
Steven
On Fri, Jul 23, 2021 at 5:16 AM Steven Lee [off-list ref] wrote:
The 07/21/2021 21:27, Bartosz Golaszewski wrote:
quoted
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee [off-list ref] wrote:
quoted
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.
For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins by dts ngpios property.
- Pair input/output GPIOs instead of using 0 as GPIO input pin base and
MAX_NR_HW_SGPIO as GPIO output pin base.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
irq_chip data.
- Replace all of_*() APIs with device_*().
Changes from v5:
* Squash v5 patch-05 and patch-06 to one patch.
* Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
input/output pin base are determined by ngpios.
For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
pin order is as follows:
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
With the new design, pin order is changed as follows:
Input:
0 2 4 6 ... 18(ngpios * 2 - 2)
Output:
1 3 5 7 ... 19(ngpios * 2 - 1)
* Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
ast2600-sgpiom.
* Fix coding style issues.
Changes from v4:
* Remove ngpios from dtsi
* Add ast2400 and ast2500 platform data.
* Remove unused macros.
* Add ngpios check in a separate patch.
* Fix coding style issues.
Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().
Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
max_ngpios.
* Split sgpio driver patch to 3 patches
Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.
Please help to review.
Thanks,
Steven
Steven Lee (9):
dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
dt-bindings: aspeed-sgpio: Add ast2600 sgpio
ARM: dts: aspeed-g6: Add SGPIO node.
ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
gpio: gpio-aspeed-sgpio: Add set_config function
gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
gpio: gpio-aspeed-sgpio: Use generic device property APIs
gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
.../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
5 files changed, 215 insertions(+), 115 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
--
2.17.1
The series looks good to me. Can the DTS and GPIO patches go into
v5.15 separately?
Hi Bart,
Thanks for the review.
Shall we do anything to make the patches go into v5.15 or wait for picking-up?
Steven
quoted
Bart
It's more of a question to the relevant SoC maintainers.
Joel, Andrew: can I take the GPIO patches through the GPIO tree and
you'll take the ARM patches separately into v5.15?
Bartosz
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee [off-list ref] wrote:
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins. Add ast2600-sgpiom compatibles and update descriptions to
introduce the max number of available gpio pins that AST2600 supported.
Signed-off-by: Steven Lee <redacted>
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee [off-list ref] wrote:
The maximum number of gpio pins of SoC is hardcoded as 80 and the gpio pin
count mask for GPIO Configuration register is hardcode as GENMASK(9,6).
However, AST2600 has 2 sgpio master interfaces, one of them supports up
to 128 gpio pins and pin count mask of GPIO Configuration Register is 5
bits.
The patch adds ast2600 compatibles, removes MAX_NR_HW_SGPIO and
corresponding design to make the gpio input/output pin base are determined
by ngpios.
The patch also removed hardcoded pin mask and adds ast2400, ast2500,
ast2600 platform data that include gpio pin count mask for GPIO
Configuration Register.
The original pin order is as follows:
(suppose MAX_NR_HW_SGPIO is 80 and ngpios is 10 as well)
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
The new pin order is as follows:
Input:
0 2 4 6 ... 18
Output:
1 3 5 7 ... 19
SGPIO pin id and input/output pin mapping is as follows:
SGPIO0(0,1), SGPIO1(2,3), ..., SGPIO79(158,159)
For example:
Access SGPIO5(10,11)
Get SGPIO pin 5 (suppose sgpio chip id is 2)
gpioget 2 10
Set SGPIO pin 5 (suppose sgpio chip id is 2)
gpioset 2 11=1
gpioset 2 11=0
Signed-off-by: Steven Lee <redacted>
Nice use of match data. This is exactly how it shall be done.
Reviewed-by: Linus Walleij <redacted>
Yours,
Linus Walleij
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On Mon, Jul 12, 2021 at 12:04 PM Steven Lee [off-list ref] wrote:
AST SoC supports *retain pin state* function when wdt reset.
The patch adds set_config function for handling sgpio reset tolerance
register.
Signed-off-by: Steven Lee <redacted>
Reviewed-by: Andrew Jeffery <redacted>
Excellent reuse of existing pin config property.
Reviewed-by: Linus Walleij <redacted>
Yours,
Linus Walleij
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On Mon, Jul 12, 2021 at 12:04 PM Steven Lee [off-list ref] wrote:
The current design initializes irq->chip from a global irqchip struct,
which causes multiple sgpio devices use the same irq_chip.
The patch moves irq_chip to aspeed_sgpio struct for initializing
irq_chip from their private gpio struct.
Signed-off-by: Steven Lee <redacted>
Reviewed-by: Andrew Jeffery <redacted>
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee [off-list ref] wrote:
Add an else-if condition in the probe function to check whether ngpios is
multiple of 8.
Per AST datasheet, numbers of available serial GPIO pins in Serial GPIO
Configuration Register must be n bytes. For instance, if n = 1, it means
AST SoC supports 8 GPIO pins.
Signed-off-by: Steven Lee <redacted>
Reviewed-by: Andrew Jeffery <redacted>
From: Andrew Jeffery <hidden> Date: 2021-08-03 04:49:19
On Fri, 23 Jul 2021, at 17:00, Bartosz Golaszewski wrote:
On Fri, Jul 23, 2021 at 5:16 AM Steven Lee [off-list ref] wrote:
quoted
The 07/21/2021 21:27, Bartosz Golaszewski wrote:
quoted
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee [off-list ref] wrote:
quoted
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.
For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins by dts ngpios property.
- Pair input/output GPIOs instead of using 0 as GPIO input pin base and
MAX_NR_HW_SGPIO as GPIO output pin base.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
irq_chip data.
- Replace all of_*() APIs with device_*().
Changes from v5:
* Squash v5 patch-05 and patch-06 to one patch.
* Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
input/output pin base are determined by ngpios.
For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
pin order is as follows:
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
With the new design, pin order is changed as follows:
Input:
0 2 4 6 ... 18(ngpios * 2 - 2)
Output:
1 3 5 7 ... 19(ngpios * 2 - 1)
* Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
ast2600-sgpiom.
* Fix coding style issues.
Changes from v4:
* Remove ngpios from dtsi
* Add ast2400 and ast2500 platform data.
* Remove unused macros.
* Add ngpios check in a separate patch.
* Fix coding style issues.
Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().
Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
max_ngpios.
* Split sgpio driver patch to 3 patches
Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.
Please help to review.
Thanks,
Steven
Steven Lee (9):
dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
dt-bindings: aspeed-sgpio: Add ast2600 sgpio
ARM: dts: aspeed-g6: Add SGPIO node.
ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
gpio: gpio-aspeed-sgpio: Add set_config function
gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
gpio: gpio-aspeed-sgpio: Use generic device property APIs
gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
.../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
5 files changed, 215 insertions(+), 115 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
--
2.17.1
The series looks good to me. Can the DTS and GPIO patches go into
v5.15 separately?
Hi Bart,
Thanks for the review.
Shall we do anything to make the patches go into v5.15 or wait for picking-up?
Steven
quoted
Bart
It's more of a question to the relevant SoC maintainers.
Joel, Andrew: can I take the GPIO patches through the GPIO tree and
you'll take the ARM patches separately into v5.15?
From: Joel Stanley <joel@jms.id.au> Date: 2021-08-03 05:58:06
On Tue, 3 Aug 2021 at 04:49, Andrew Jeffery [off-list ref] wrote:
On Fri, 23 Jul 2021, at 17:00, Bartosz Golaszewski wrote:
quoted
Joel, Andrew: can I take the GPIO patches through the GPIO tree and
you'll take the ARM patches separately into v5.15?
I think that should be okay. I'll poke Joel.
Yes, that's fine. I have merged the first four patches into the aspeed tree.
Cheers,
Joel
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