[PATCH v2 0/3] add one regulator used to power up pcie phy

STALE1957d

Revision v2 of 3 in this series.

7 messages, 2 authors, 2021-03-25 · open the first message on its own page

[PATCH v2 0/3] add one regulator used to power up pcie phy

From: Richard Zhu <hongxing.zhu@nxp.com>
Date: 2021-03-24 05:48:47

Changes:
v1 --> v2:
Suggested by Lucas, don't use the boolean property to specify the
different power supplies to PCIe PHY.
Use one regulator to power up PCIe PHY, and the regulator APIs to
get the voltage of it.

[PATCH v2 1/3] dt-bindings: imx6q-pcie: add one regulator used to
[PATCH v2 2/3] arm64: dts: imx8mq-evk: add one regulator used to
[PATCH v2 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is

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[PATCH v2 2/3] arm64: dts: imx8mq-evk: add one regulator used to power up pcie phy

From: Richard Zhu <hongxing.zhu@nxp.com>
Date: 2021-03-24 05:48:47

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 85b045253a0e..4d2035e3dd7c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts

@@ -318,6 +318,7 @@
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
 		 <&pcie0_refclk>;
 	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	vph-supply = <&vgen5_reg>;
 	status = "okay";
 };

-- 
2.17.1


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[PATCH v2 1/3] dt-bindings: imx6q-pcie: add one regulator used to power up pcie phy

From: Richard Zhu <hongxing.zhu@nxp.com>
Date: 2021-03-24 05:48:47

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index de4b2baf91e8..3248b7192ced 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt

@@ -38,6 +38,12 @@ Optional properties:
   The regulator will be enabled when initializing the PCIe host and
   disabled either as part of the init process or when shutting down the
   host.
+- vph-supply: Should specify the regulator in charge of PCIe PHY power.
+  On i.MX8MQ, both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe
+  PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
+  sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the
+  VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1
+  to 1b'0.
 
 Additional required properties for imx6sx-pcie:
 - clock names: Must include the following additional entries:

-- 
2.17.1


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Re: [PATCH v2 1/3] dt-bindings: imx6q-pcie: add one regulator used to power up pcie phy

From: Lucas Stach <l.stach@pengutronix.de>
Date: 2021-03-24 09:28:08

Hi Richard,

Am Mittwoch, dem 24.03.2021 um 13:34 +0800 schrieb Richard Zhu:

quoted hunk

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index de4b2baf91e8..3248b7192ced 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt

@@ -38,6 +38,12 @@ Optional properties:

   The regulator will be enabled when initializing the PCIe host and
   disabled either as part of the init process or when shutting down the
   host.
+- vph-supply: Should specify the regulator in charge of PCIe PHY power.
+  On i.MX8MQ, both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe
+  PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
+  sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the
+  VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1
+  to 1b'0.

This description of the internal driver behavior does not belong into a
DT binding description.
Instead the binding should describe the function of the regulator
exactly. From the datasheet I can see that there are actually 3
supplies (VPH, VP, VPTX) going into the PCIe PHY, so "regulator in
charge of PCIe PHY power" doesn't seem like a very accurate
description.

Regards,
Lucas


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[PATCH v2 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is 3v3

From: Richard Zhu <hongxing.zhu@nxp.com>
Date: 2021-03-24 05:48:47

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 853ea8e82952..beca085a9300 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c

@@ -37,6 +37,7 @@
 #define IMX8MQ_GPR_PCIE_REF_USE_PAD		BIT(9)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN	BIT(10)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE	BIT(11)
+#define IMX8MQ_GPR_PCIE_VREG_BYPASS		BIT(12)
 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE	GENMASK(11, 8)
 #define IMX8MQ_PCIE2_BASE_ADDR			0x33c00000

@@ -80,6 +81,7 @@ struct imx6_pcie {
 	u32			tx_swing_full;
 	u32			tx_swing_low;
 	struct regulator	*vpcie;
+	struct regulator	*vph;
 	void __iomem		*phy_base;
 
 	/* power domain for pcie */

@@ -611,6 +613,8 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 
 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 {
+	int phy_uv;
+
 	switch (imx6_pcie->drvdata->variant) {
 	case IMX8MQ:
 		/*

@@ -621,6 +625,18 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 				   imx6_pcie_grp_offset(imx6_pcie),
 				   IMX8MQ_GPR_PCIE_REF_USE_PAD,
 				   IMX8MQ_GPR_PCIE_REF_USE_PAD);
+		/*
+		 * Regarding to the datasheet, the PCIE_VPH is suggested
+		 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
+		 * VREG_BYPASS should be cleared to zero.
+		 */
+		if (imx6_pcie->vph)
+			phy_uv = regulator_get_voltage(imx6_pcie->vph);
+		if (phy_uv > 3000000)
+			regmap_update_bits(imx6_pcie->iomuxc_gpr,
+					   imx6_pcie_grp_offset(imx6_pcie),
+					   IMX8MQ_GPR_PCIE_VREG_BYPASS,
+					   0);
 		break;
 	case IMX7D:
 		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,

@@ -1130,6 +1146,13 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 		imx6_pcie->vpcie = NULL;
 	}
 
+	imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
+	if (IS_ERR(imx6_pcie->vph)) {
+		if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
+			return PTR_ERR(imx6_pcie->vph);
+		imx6_pcie->vph = NULL;
+	}
+
 	platform_set_drvdata(pdev, imx6_pcie);
 
 	ret = imx6_pcie_attach_pd(dev);

-- 
2.17.1


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Re: [PATCH v2 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is 3v3

From: Lucas Stach <l.stach@pengutronix.de>
Date: 2021-03-24 09:31:22

Am Mittwoch, dem 24.03.2021 um 13:34 +0800 schrieb Richard Zhu:

quoted hunk

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 853ea8e82952..beca085a9300 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c

@@ -37,6 +37,7 @@

 #define IMX8MQ_GPR_PCIE_REF_USE_PAD		BIT(9)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN	BIT(10)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE	BIT(11)
+#define IMX8MQ_GPR_PCIE_VREG_BYPASS		BIT(12)
 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE	GENMASK(11, 8)
 #define IMX8MQ_PCIE2_BASE_ADDR			0x33c00000

@@ -80,6 +81,7 @@ struct imx6_pcie {

 	u32			tx_swing_full;
 	u32			tx_swing_low;
 	struct regulator	*vpcie;
+	struct regulator	*vph;
 	void __iomem		*phy_base;
 



 	/* power domain for pcie */

@@ -611,6 +613,8 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)

 



 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 {
+	int phy_uv;
+

No need for this variable...

quoted hunk

 	switch (imx6_pcie->drvdata->variant) {
 	case IMX8MQ:
 		/*

@@ -621,6 +625,18 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)

 				   imx6_pcie_grp_offset(imx6_pcie),
 				   IMX8MQ_GPR_PCIE_REF_USE_PAD,
 				   IMX8MQ_GPR_PCIE_REF_USE_PAD);
+		/*
+		 * Regarding to the datasheet, the PCIE_VPH is suggested
+		 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
+		 * VREG_BYPASS should be cleared to zero.
+		 */
+		if (imx6_pcie->vph)
+			phy_uv = regulator_get_voltage(imx6_pcie->vph);
+		if (phy_uv > 3000000)
+			regmap_update_bits(imx6_pcie->iomuxc_gpr,
+					   imx6_pcie_grp_offset(imx6_pcie),
+					   IMX8MQ_GPR_PCIE_VREG_BYPASS,
+					   0);

...if you just fold this into a single condition. Right now phy_uv
might be used uninitialized when the vph-supply is not specified in the
DT. Better write this as:

if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000)

Regards,
Lucas

quoted hunk

 		break;
 	case IMX7D:
 		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,

@@ -1130,6 +1146,13 @@ static int imx6_pcie_probe(struct platform_device *pdev)

 		imx6_pcie->vpcie = NULL;
 	}
 







+	imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
+	if (IS_ERR(imx6_pcie->vph)) {
+		if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
+			return PTR_ERR(imx6_pcie->vph);
+		imx6_pcie->vph = NULL;
+	}
+
 	platform_set_drvdata(pdev, imx6_pcie);
 







 	ret = imx6_pcie_attach_pd(dev);



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RE: [EXT] Re: [PATCH v2 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is 3v3

From: Richard Zhu <hongxing.zhu@nxp.com>
Date: 2021-03-25 02:23:09

-----Original Message-----
From: Lucas Stach <l.stach@pengutronix.de>
Sent: Wednesday, March 24, 2021 5:30 PM
To: Richard Zhu <hongxing.zhu@nxp.com>; andrew.smirnov@gmail.com;
shawnguo@kernel.org; kw@linux.com; bhelgaas@google.com;
stefan@agner.ch; lorenzo.pieralisi@arm.com
Cc: linux-pci@vger.kernel.org; dl-linux-imx <redacted>;
linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
kernel@pengutronix.de
Subject: Re: [PATCH v2 3/3] PCI: imx: clear vreg bypass when pcie vph
voltage is 3v3
Am Mittwoch, dem 24.03.2021 um 13:34 +0800 schrieb Richard Zhu:

quoted

Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
turned on.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c

b/drivers/pci/controller/dwc/pci-imx6.c
index 853ea8e82952..beca085a9300 100644

--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c

@@ -37,6 +37,7 @@
 #define IMX8MQ_GPR_PCIE_REF_USE_PAD          BIT(9)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN  BIT(10)
 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE     BIT(11)
+#define IMX8MQ_GPR_PCIE_VREG_BYPASS          BIT(12)
 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE  GENMASK(11, 8)
 #define IMX8MQ_PCIE2_BASE_ADDR

0x33c00000

quoted

@@ -80,6 +81,7 @@ struct imx6_pcie {
      u32                     tx_swing_full;
      u32                     tx_swing_low;
      struct regulator        *vpcie;
+     struct regulator        *vph;
      void __iomem            *phy_base;




      /* power domain for pcie */
@@ -611,6 +613,8 @@ static void imx6_pcie_configure_type(struct

imx6_pcie *imx6_pcie)




 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)  {
+     int phy_uv;
+

No need for this variable...

[Richard Zhu] Thanks, would be removed later.

quoted

      switch (imx6_pcie->drvdata->variant) {
      case IMX8MQ:
              /*

@@ -621,6 +625,18 @@ static void imx6_pcie_init_phy(struct imx6_pcie

*imx6_pcie)

quoted

                                 imx6_pcie_grp_offset(imx6_pcie),

IMX8MQ_GPR_PCIE_REF_USE_PAD,

quoted

IMX8MQ_GPR_PCIE_REF_USE_PAD);

quoted

+             /*
+              * Regarding to the datasheet, the PCIE_VPH is suggested
+              * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
+              * VREG_BYPASS should be cleared to zero.
+              */
+             if (imx6_pcie->vph)
+                     phy_uv =

regulator_get_voltage(imx6_pcie->vph);

quoted

+             if (phy_uv > 3000000)
+                     regmap_update_bits(imx6_pcie->iomuxc_gpr,
+

imx6_pcie_grp_offset(imx6_pcie),

quoted

IMX8MQ_GPR_PCIE_VREG_BYPASS,

quoted

+                                        0);

...if you just fold this into a single condition. Right now phy_uv might be used
uninitialized when the vph-supply is not specified in the DT. Better write this
as:

if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000)

[Richard Zhu] Thanks. Would be changed as this way.

Regards,
Lucas

quoted

              break;
      case IMX7D:
              regmap_update_bits(imx6_pcie->iomuxc_gpr,

IOMUXC_GPR12,

quoted

@@ -1130,6 +1146,13 @@ static int imx6_pcie_probe(struct

platform_device *pdev)

quoted

              imx6_pcie->vpcie = NULL;
      }








+     imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev,

"vph");

quoted

+     if (IS_ERR(imx6_pcie->vph)) {
+             if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
+                     return PTR_ERR(imx6_pcie->vph);
+             imx6_pcie->vph = NULL;
+     }
+
      platform_set_drvdata(pdev, imx6_pcie);








      ret = imx6_pcie_attach_pd(dev);

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