From: Samuel Holland <samuel@sholland.org> Date: 2021-03-15 04:33:48
The sun4i timer IP block has a variable number of interrupts based on
the compatible. Use enums to combine the two sections for the existing
3-interrupt variants, and to simplify adding new compatible strings.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 25 ++++++-------------
1 file changed, 7 insertions(+), 18 deletions(-)
From: Samuel Holland <samuel@sholland.org> Date: 2021-03-15 04:33:48
The sun50i SoCs contain timer blocks which are useful as broadcast
clockevent sources. They each have 2 interrupts, matching the A23
variant, so add the new compatible strings with the A23 compatible
as a fallback.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
From: Samuel Holland <samuel@sholland.org> Date: 2021-03-15 04:33:48
Nodes should be sorted by unit address. Move the watchdog node to the
correct place, so it will be next to the timer node when that is added.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
From: Samuel Holland <samuel@sholland.org> Date: 2021-03-15 04:33:49
For a CPU to enter an idle state, there must be some timer which can
trigger an IRQ to wake it back up. The local ARM architectural timer is
not sufficient, because that timer stops when the CPU is powered down.
Some other CPU's ARM architectural timer can be used, but this prevents
that other CPU from entering an idle state. So to allow all CPUs to
enter an idle state at the same time, some MMIO timer must be available
that is not tied to any CPU.
The basic "sun4i" timer seems most appropriate for this purpose due to
its moderate rate, balancing precision and power consumption.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++
3 files changed, 27 insertions(+)
From: Samuel Holland <samuel@sholland.org> Date: 2021-03-15 04:33:49
While the ARM architectural timer is generatlly the best timer to use,
a non-c3stop timer is needed for cpuidle. Use the sun4i timer for this
purpose, which is present on all 64-bit sunxi SoCs.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
From: Maxime Ripard <hidden> Date: 2021-03-15 10:58:59
On Sun, Mar 14, 2021 at 11:32:46PM -0500, Samuel Holland wrote:
The sun4i timer IP block has a variable number of interrupts based on
the compatible. Use enums to combine the two sections for the existing
3-interrupt variants, and to simplify adding new compatible strings.
Signed-off-by: Samuel Holland <samuel@sholland.org>
From: Maxime Ripard <hidden> Date: 2021-03-15 11:08:40
On Sun, Mar 14, 2021 at 11:32:47PM -0500, Samuel Holland wrote:
The sun50i SoCs contain timer blocks which are useful as broadcast
clockevent sources. They each have 2 interrupts, matching the A23
variant, so add the new compatible strings with the A23 compatible
as a fallback.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Hi!
Dne ponedeljek, 15. marec 2021 ob 05:32:49 CET je Samuel Holland napisal(a):
quoted hunk
For a CPU to enter an idle state, there must be some timer which can
trigger an IRQ to wake it back up. The local ARM architectural timer is
not sufficient, because that timer stops when the CPU is powered down.
Some other CPU's ARM architectural timer can be used, but this prevents
that other CPU from entering an idle state. So to allow all CPUs to
enter an idle state at the same time, some MMIO timer must be available
that is not tied to any CPU.
The basic "sun4i" timer seems most appropriate for this purpose due to
its moderate rate, balancing precision and power consumption.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++
3 files changed, 27 insertions(+)
From: Samuel Holland <samuel@sholland.org> Date: 2021-03-16 04:36:41
On 3/15/21 1:32 PM, Jernej Škrabec wrote:
Hi!
Dne ponedeljek, 15. marec 2021 ob 05:32:49 CET je Samuel Holland napisal(a):
quoted
For a CPU to enter an idle state, there must be some timer which can
trigger an IRQ to wake it back up. The local ARM architectural timer is
not sufficient, because that timer stops when the CPU is powered down.
Some other CPU's ARM architectural timer can be used, but this prevents
that other CPU from entering an idle state. So to allow all CPUs to
enter an idle state at the same time, some MMIO timer must be available
that is not tied to any CPU.
The basic "sun4i" timer seems most appropriate for this purpose due to
its moderate rate, balancing precision and power consumption.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 9 +++++++++
3 files changed, 27 insertions(+)