Re: [PATCH v5 0/4] perf vendor events: Support PMU events for A64FX

On 10/02/2021 15:34, nakamura.shun@fujitsu.com wrote:

Hi, John

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So my series is now on remotes/origin/tmp.perf/core in Arnaldo's acme git, so

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you could resend against that.

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https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git

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Or again, put my series on perf/core and send against that.

I will resend based on tmp.perf/core.

Actually it is now on perf/core, so that is a better baseline.

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As for patch 3/4, firstly I'd say that it is not a 'fix'. As well, please ensure it causes

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no regression on x86 or arm64. So like "perf list" output is same as before (with

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just that change), and also test some same perf events and metrics (x86 only) to

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ensure that they are ok.

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Please also ensure no regression on "perf test".

I will fix the subject of patch 3/4.

I have checked the following:

- perf list does not change for x86 and A64FX

- No regression on perf test

- No problem with FLOPs and PMU event counters on x86

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BTW, please config your mail client for no text encoding.

I will send it in HTML format.

Hmmm, that's not better. I think that the mail servers reject html.

Please consult Documentation/process/email-clients.rst

Thanks,
John


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Hi, John

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I will resend based on tmp.perf/core.

Actually it is now on perf/core, so that is a better baseline.

I will resend based on perf/core.

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I will send it in HTML format.

Hmmm, that's not better. I think that the mail servers reject html.

Please consult Documentation/process/email-clients.rst

Thanks for the info.

Best Regards
Shunsuke

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