Align the compatible strings with the board binding defined in schema
file.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a-tsn.dts | 1 +
arch/arm/boot/dts/ls1021a.dtsi | 1 -
2 files changed, 1 insertion(+), 1 deletion(-)
Replace the license text with SPDX identifiers. In the mean while
updated copyright years for previous changes.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a-qds.dts | 46 ++-----------------------------
arch/arm/boot/dts/ls1021a-twr.dts | 46 ++-----------------------------
arch/arm/boot/dts/ls1021a.dtsi | 45 ++----------------------------
3 files changed, 6 insertions(+), 131 deletions(-)
There is no regulator bus in hardware. So move the regulator nodes out
and remove the regulators simple-bus. This also make the dts align with
the simple-bus schema.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a-qds.dts | 19 ++++++-------------
arch/arm/boot/dts/ls1021a-twr.dts | 19 ++++++-------------
2 files changed, 12 insertions(+), 26 deletions(-)
Add the missing board in the binding docuemnt.
Signed-off-by: Li Yang <redacted>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
Break up long values to pass dt-schema checks.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
Breakup long values in the ifc node. Change the node name to ifc-bus to
follow the schema of simple-bus and disable the bus in the SoC dtsi file
to be enabled only in board dts files.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a-qds.dts | 6 +++---
arch/arm/boot/dts/ls1021a.dtsi | 3 ++-
2 files changed, 5 insertions(+), 4 deletions(-)
Fix the following error from "make dtbs_check"
memory: False schema does not allow ...
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Breakup long values to pass the schema check.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a.dtsi | 72 +++++++++++++++++-----------------
1 file changed, 36 insertions(+), 36 deletions(-)
Property "postion" is not documented in the mma8452 binding. Remove it
to resolve the error in "make dtbs_check"
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a-tsn.dts | 1 -
1 file changed, 1 deletion(-)
Convert the txt binding to yaml format and add description. Also
updated the recommended node name to ifc-bus to align with the
simple-bus node name requirements.
Signed-off-by: Li Yang <redacted>
---
.../bindings/memory-controllers/fsl/ifc.txt | 82 ----------
.../bindings/memory-controllers/fsl/ifc.yaml | 140 ++++++++++++++++++
2 files changed, 140 insertions(+), 82 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml
@@ -1,82 +0,0 @@-Integrated Flash Controller--Properties:-- name : Should be ifc-- compatible : should contain "fsl,ifc". The version of the integrated- flash controller can be found in the IFC_REV register at- offset zero.--- #address-cells : Should be either two or three. The first cell is the- chipselect number, and the remaining cells are the- offset into the chipselect.-- #size-cells : Either one or two, depending on how large each chipselect- can be.-- reg : Offset and length of the register set for the device-- interrupts: IFC may have one or two interrupts. If two interrupt- specifiers are present, the first is the "common"- interrupt (CM_EVTER_STAT), and the second is the NAND- interrupt (NAND_EVTER_STAT). If there is only one,- that interrupt reports both types of event.--- little-endian : If this property is absent, the big-endian mode will- be in use as default for registers.--- ranges : Each range corresponds to a single chipselect, and covers- the entire access window as configured.--Child device nodes describe the devices connected to IFC such as NOR (e.g.-cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices-like FPGAs, CPLDs, etc.--Example:-- ifc@ffe1e000 {- compatible = "fsl,ifc", "simple-bus";- #address-cells = <2>;- #size-cells = <1>;- reg = <0x0 0xffe1e000 0 0x2000>;- interrupts = <16 2 19 2>;- little-endian;-- /* NOR, NAND Flashes and CPLD on board */- ranges = <0x0 0x0 0x0 0xee000000 0x02000000- 0x1 0x0 0x0 0xffa00000 0x00010000- 0x3 0x0 0x0 0xffb00000 0x00020000>;-- flash@0,0 {- #address-cells = <1>;- #size-cells = <1>;- compatible = "cfi-flash";- reg = <0x0 0x0 0x2000000>;- bank-width = <2>;- device-width = <1>;-- partition@0 {- /* 32MB for user data */- reg = <0x0 0x02000000>;- label = "NOR Data";- };- };-- flash@1,0 {- #address-cells = <1>;- #size-cells = <1>;- compatible = "fsl,ifc-nand";- reg = <0x1 0x0 0x10000>;-- partition@0 {- /* This location must not be altered */- /* 1MB for u-boot Bootloader Image */- reg = <0x0 0x00100000>;- label = "NAND U-Boot Image";- read-only;- };- };-- cpld@3,0 {- #address-cells = <1>;- #size-cells = <1>;- compatible = "fsl,p1010rdb-cpld";- reg = <0x3 0x0 0x000001f>;- };- };
@@ -0,0 +1,140 @@+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)+%YAML1.2+---+$id:http://devicetree.org/schemas/memory-controllers/fsl/ifc.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:FSL/NXP Integrated Flash Controller++maintainers:+-Li Yang <leoyang.li@nxp.com>++description:|+NXP's integrated flash controller (IFC) is an advanced version of the+enhanced local bus controller which includes similar programming and signal+interfaces with an extended feature set. The IFC provides access to multiple+external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,+SRAM and other memories where address and data are shared on a bus.++allOf:+-$ref:/schemas/simple-bus.yaml#++properties:+$nodename:+pattern:"^ifc-bus@[0-9a-f]+$"++compatible:+contains:+const:fsl,ifc++"#address-cells":+enum:[2,3]+description:|+Should be either two or three. The first cell is the chipselect+number, and the remaining cells are the offset into the chipselect.++"#size-cells":+enum:[1,2]+description:|+Either one or two, depending on how large each chipselect can be.++reg:+maxItems:1+description:|+Offset and length of the register set for the device.++interrupts:+minItems:1+maxItems:2+description:|+IFC may have one or two interrupts. If two interrupt specifiers are+present, the first is the "common" interrupt (CM_EVTER_STAT), and the+second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,+that interrupt reports both types of event.++little-endian:+description:|+If this property is absent, the big-endian mode will be in use as default+for registers.++ranges:+description:|+Each range corresponds to a single chipselect, and covers the entire+access window as configured.++patternProperties:+"^.*@[a-f0-9]+(,[a-f0-9]+)+$":+type:object+description:|+Child device nodes describe the devices connected to IFC such as NOR (e.g.+cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices+like FPGAs, CPLDs, etc.++required:+-compatible+-reg++required:+-compatible+-reg+-interrupts++additionalProperties:false++examples:+-|+soc {+#address-cells = <2>;+#size-cells = <2>;++ifc-bus@ffe1e000 {+compatible = "fsl,ifc", "simple-bus";+#address-cells = <2>;+#size-cells = <1>;+reg = <0x0 0xffe1e000 0 0x2000>;+interrupts = <16 2 19 2>;+little-endian;++/* NOR, NAND Flashes and CPLD on board */+ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,+<0x1 0x0 0x0 0xffa00000 0x00010000>,+<0x3 0x0 0x0 0xffb00000 0x00020000>;++flash@0,0 {+#address-cells = <1>;+#size-cells = <1>;+compatible = "cfi-flash";+reg = <0x0 0x0 0x2000000>;+bank-width = <2>;+device-width = <1>;++partition@0 {+/* 32MB for user data */+reg = <0x0 0x02000000>;+label = "NOR Data";+};+};++flash@1,0 {+#address-cells = <1>;+#size-cells = <1>;+compatible = "fsl,ifc-nand";+reg = <0x1 0x0 0x10000>;++partition@0 {+/* This location must not be altered */+/* 1MB for u-boot Bootloader Image */+reg = <0x0 0x00100000>;+label = "NAND U-Boot Image";+read-only;+};+};++cpld@3,0 {+#address-cells = <1>;+#size-cells = <1>;+compatible = "fsl,p1010rdb-cpld";+reg = <0x3 0x0 0x000001f>;+};+};+};
--
2.17.1
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Add the #power-domain-cells for power-controller node as required by the
schema.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a.dtsi | 1 +
1 file changed, 1 insertion(+)
Layerscape SoCs doesn't use ipg as clock name. Remove the clock name
requirement in the schema. Also the original binding doesn't enforce
the order of "tx" and "rx" in dma-names. Both orders are used
extensively in existing dtses, update the schema to allow both.
Signed-off-by: Li Yang <redacted>
---
Documentation/devicetree/bindings/i2c/i2c-imx.yaml | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
@@ -54,20 +54,19 @@ properties:maxItems:1clock-names:-const:ipg+maxItems:1clock-frequency:enum:[100000,400000]dmas:-items:--description:DMA controller phandle and request line for RX--description:DMA controller phandle and request line for TX+minItems:2+maxItems:2dma-names:items:--const:rx--const:tx+-enum:["rx","tx"]+-enum:["tx","rx"]sda-gpios:maxItems:1
--
2.17.1
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The FPGA is not really a bus but more like an MFD device. Change the
compatible string from "simple-bus" to "simple-mfd". This also fix a
node name issue with simple-bus schema.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a-qds.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Add the #dma-cells to align with the dma schema.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a.dtsi | 1 +
1 file changed, 1 insertion(+)
From: Krzysztof Kozlowski <krzk@kernel.org> Date: 2021-02-06 11:23:51
On Fri, Feb 05, 2021 at 05:47:20PM -0600, Li Yang wrote:
Add the missing board in the binding docuemnt.
It's not necessarily missing as there are no DTS (in tree) using this
compatible, so maybe rephrase it to:
"Add board compatible for ls1021a-tsn board".
Best regards,
Krzysztof
Signed-off-by: Li Yang <redacted>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
From: Krzysztof Kozlowski <krzk@kernel.org> Date: 2021-02-06 11:28:34
On Fri, Feb 05, 2021 at 05:47:21PM -0600, Li Yang wrote:
quoted hunk
Layerscape SoCs doesn't use ipg as clock name. Remove the clock name
requirement in the schema. Also the original binding doesn't enforce
the order of "tx" and "rx" in dma-names. Both orders are used
extensively in existing dtses, update the schema to allow both.
Signed-off-by: Li Yang <redacted>
---
Documentation/devicetree/bindings/i2c/i2c-imx.yaml | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
No, for other SoCs the clock is I think required, so it should be there.
Add an allof-if statements to require it on specific compatibles and
skip on others.
No, the order should be enforced. That was a generic recommendation from
Rob.
Also, I don't get the what does it mean "the original binding" in commit
msg. This is the original binding. Upstream. Mainline.
If your DTSes have different order, please adjust them, not the binding.
Best regards,
Krzysztof
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From: Krzysztof Kozlowski <krzk@kernel.org> Date: 2021-02-06 11:38:21
On Fri, Feb 05, 2021 at 05:47:22PM -0600, Li Yang wrote:
quoted hunk
Convert the txt binding to yaml format and add description. Also
updated the recommended node name to ifc-bus to align with the
simple-bus node name requirements.
Signed-off-by: Li Yang <redacted>
---
.../bindings/memory-controllers/fsl/ifc.txt | 82 ----------
.../bindings/memory-controllers/fsl/ifc.yaml | 140 ++++++++++++++++++
2 files changed, 140 insertions(+), 82 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml
@@ -1,82 +0,0 @@-Integrated Flash Controller--Properties:-- name : Should be ifc-- compatible : should contain "fsl,ifc". The version of the integrated- flash controller can be found in the IFC_REV register at- offset zero.--- #address-cells : Should be either two or three. The first cell is the- chipselect number, and the remaining cells are the- offset into the chipselect.-- #size-cells : Either one or two, depending on how large each chipselect- can be.-- reg : Offset and length of the register set for the device-- interrupts: IFC may have one or two interrupts. If two interrupt- specifiers are present, the first is the "common"- interrupt (CM_EVTER_STAT), and the second is the NAND- interrupt (NAND_EVTER_STAT). If there is only one,- that interrupt reports both types of event.--- little-endian : If this property is absent, the big-endian mode will- be in use as default for registers.--- ranges : Each range corresponds to a single chipselect, and covers- the entire access window as configured.--Child device nodes describe the devices connected to IFC such as NOR (e.g.-cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices-like FPGAs, CPLDs, etc.--Example:-- ifc@ffe1e000 {- compatible = "fsl,ifc", "simple-bus";- #address-cells = <2>;- #size-cells = <1>;- reg = <0x0 0xffe1e000 0 0x2000>;- interrupts = <16 2 19 2>;- little-endian;-- /* NOR, NAND Flashes and CPLD on board */- ranges = <0x0 0x0 0x0 0xee000000 0x02000000- 0x1 0x0 0x0 0xffa00000 0x00010000- 0x3 0x0 0x0 0xffb00000 0x00020000>;-- flash@0,0 {- #address-cells = <1>;- #size-cells = <1>;- compatible = "cfi-flash";- reg = <0x0 0x0 0x2000000>;- bank-width = <2>;- device-width = <1>;-- partition@0 {- /* 32MB for user data */- reg = <0x0 0x02000000>;- label = "NOR Data";- };- };-- flash@1,0 {- #address-cells = <1>;- #size-cells = <1>;- compatible = "fsl,ifc-nand";- reg = <0x1 0x0 0x10000>;-- partition@0 {- /* This location must not be altered */- /* 1MB for u-boot Bootloader Image */- reg = <0x0 0x00100000>;- label = "NAND U-Boot Image";- read-only;- };- };-- cpld@3,0 {- #address-cells = <1>;- #size-cells = <1>;- compatible = "fsl,p1010rdb-cpld";- reg = <0x3 0x0 0x000001f>;- };- };
@@ -0,0 +1,140 @@+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)+%YAML1.2+---+$id:http://devicetree.org/schemas/memory-controllers/fsl/ifc.yaml#+$schema:http://devicetree.org/meta-schemas/core.yaml#++title:FSL/NXP Integrated Flash Controller++maintainers:+-Li Yang <leoyang.li@nxp.com>++description:|+NXP's integrated flash controller (IFC) is an advanced version of the+enhanced local bus controller which includes similar programming and signal+interfaces with an extended feature set. The IFC provides access to multiple+external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,+SRAM and other memories where address and data are shared on a bus.++allOf:+-$ref:/schemas/simple-bus.yaml#++properties:+$nodename:+pattern:"^ifc-bus@[0-9a-f]+$"
Just "bus". The node name should be generic, represent generic class of
a device. The class is a bus.
+
+ compatible:
+ contains:
+ const: fsl,ifc
I think you should list all compatibles, to be specific. "contains"
allow adding any arbitrary compatible.
+
+ "#address-cells":
+ enum: [2, 3]
+ description: |
+ Should be either two or three. The first cell is the chipselect
+ number, and the remaining cells are the offset into the chipselect.
+
+ "#size-cells":
+ enum: [1, 2]
+ description: |
+ Either one or two, depending on how large each chipselect can be.
+
+ reg:
+ maxItems: 1
+ description: |
+ Offset and length of the register set for the device.
Wrong indentation.
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ description: |
+ IFC may have one or two interrupts. If two interrupt specifiers are
+ present, the first is the "common" interrupt (CM_EVTER_STAT), and the
+ second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,
+ that interrupt reports both types of event.
+
+ little-endian:
+ description: |
+ If this property is absent, the big-endian mode will be in use as default
+ for registers.
type: boolean
+
+ ranges:
+ description: |
+ Each range corresponds to a single chipselect, and covers the entire
+ access window as configured.
+
+patternProperties:
From: Krzysztof Kozlowski <krzk@kernel.org> Date: 2021-02-06 11:43:47
On Fri, Feb 05, 2021 at 05:47:23PM -0600, Li Yang wrote:
quoted hunk
Replace the license text with SPDX identifiers. In the mean while
updated copyright years for previous changes.
Signed-off-by: Li Yang <redacted>
---
arch/arm/boot/dts/ls1021a-qds.dts | 46 ++-----------------------------
arch/arm/boot/dts/ls1021a-twr.dts | 46 ++-----------------------------
arch/arm/boot/dts/ls1021a.dtsi | 45 ++----------------------------
3 files changed, 6 insertions(+), 131 deletions(-)
@@ -1,49 +1,7 @@+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)/**Copyright2013-2014FreescaleSemiconductor,Inc.-*Copyright2018NXP
Please split the copyright update. Adding a SPDX is not big enough to
justify adding new copyrights. On the other hand, if NXP contributed
over time and you want to reflect it in the copyrights, it's a different
path.
quoted hunk
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright 2018-2021 NXP
*/
/dts-v1/;
@@ -1,48 +1,7 @@+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)/**Copyright2013-2014FreescaleSemiconductor,Inc.-*-*Thisfileisdual-licensed:youcanuseiteitherundertheterms-*oftheGPLortheX11license,atyouroption.Notethatthisdual-*licensingonlyappliestothisfile,andnotthisprojectasa-*whole.-*-*a)Thisfileisfreesoftware;youcanredistributeitand/or-*modifyitunderthetermsoftheGNUGeneralPublicLicenseas-*publishedbytheFreeSoftwareFoundation;eitherversion2of-*theLicense,or(atyouroption)anylaterversion.-*-*Thisfileisdistributedinthehopethatitwillbeuseful,-*butWITHOUTANYWARRANTY;withouteventheimpliedwarrantyof-*MERCHANTABILITYorFITNESSFORAPARTICULARPURPOSE.Seethe-*GNUGeneralPublicLicenseformoredetails.-*-*YoushouldhavereceivedacopyoftheGNUGeneralPublic-*Licensealongwiththisfile;ifnot,writetotheFree-*SoftwareFoundation,Inc.,51FranklinSt,FifthFloor,Boston,-*MA02110-1301USA-*-*Or,alternatively,-*-*b)Permissionisherebygranted,freeofcharge,toanyperson-*obtainingacopyofthissoftwareandassociateddocumentation-*files(the"Software"),todealintheSoftwarewithout-*restriction,includingwithoutlimitationtherightstouse,-*copy,modify,merge,publish,distribute,sublicense,and/or-*sellcopiesoftheSoftware,andtopermitpersonstowhomthe-*Softwareisfurnishedtodoso,subjecttothefollowing-*conditions:-*-*Theabovecopyrightnoticeandthispermissionnoticeshallbe-*includedinallcopiesorsubstantialportionsoftheSoftware.-*-*THESOFTWAREISPROVIDED"AS IS",WITHOUTWARRANTYOFANYKIND,-*EXPRESSORIMPLIED,INCLUDINGBUTNOTLIMITEDTOTHEWARRANTIES-*OFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSEAND-*NONINFRINGEMENT.INNOEVENTSHALLTHEAUTHORSORCOPYRIGHT-*HOLDERSBELIABLEFORANYCLAIM,DAMAGESOROTHERLIABILITY,-*WHETHERINANACTIONOFCONTRACT,TORTOROTHERWISE,ARISING-*FROM,OUTOFORINCONNECTIONWITHTHESOFTWAREORTHEUSEOR-*OTHERDEALINGSINTHESOFTWARE.+*Copyright2015-2021NXP
Srsly, you even add here entirely new copyrights hidden under a SPDX
change.
No, it's not the way to do it.
Best regards,
Krzysztof
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From: Rob Herring <robh@kernel.org> Date: 2021-02-08 18:48:27
On Fri, 05 Feb 2021 17:47:22 -0600, Li Yang wrote:
Convert the txt binding to yaml format and add description. Also
updated the recommended node name to ifc-bus to align with the
simple-bus node name requirements.
Signed-off-by: Li Yang <redacted>
---
.../bindings/memory-controllers/fsl/ifc.txt | 82 ----------
.../bindings/memory-controllers/fsl/ifc.yaml | 140 ++++++++++++++++++
2 files changed, 140 insertions(+), 82 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.example.dts:36.27-49.19: Warning (simple_bus_reg): /example-0/soc/ifc-bus@ffe1e000/flash@0,0: simple-bus unit address format error, expected "0"
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.example.dts:51.27-64.19: Warning (simple_bus_reg): /example-0/soc/ifc-bus@ffe1e000/flash@1,0: simple-bus unit address format error, expected "100000000"
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.example.dts:66.26-71.19: Warning (simple_bus_reg): /example-0/soc/ifc-bus@ffe1e000/cpld@3,0: simple-bus unit address format error, expected "300000000"
See https://patchwork.ozlabs.org/patch/1436960
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
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-----Original Message-----
From: Rob Herring <robh@kernel.org>
Sent: Monday, February 8, 2021 10:55 AM
To: Leo Li <redacted>
Cc: linux-arm-kernel@lists.infradead.org; Oleksij Rempel <linux@rempel-
privat.de>; Rob Herring [off-list ref]; Krzysztof Kozlowski
[off-list ref]; devicetree@vger.kernel.org; linux-
kernel@vger.kernel.org; Shawn Guo [off-list ref]
Subject: Re: [PATCH 03/15] dt-bindings: memory: fsl: convert ifc binding to
yaml schema
On Fri, 05 Feb 2021 17:47:22 -0600, Li Yang wrote:
quoted
Convert the txt binding to yaml format and add description. Also
updated the recommended node name to ifc-bus to align with the
simple-bus node name requirements.
Signed-off-by: Li Yang <redacted>
---
.../bindings/memory-controllers/fsl/ifc.txt | 82 ----------
.../bindings/memory-controllers/fsl/ifc.yaml | 140
++++++++++++++++++
2 files changed, 140 insertions(+), 82 deletions(-) delete mode
100644
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
create mode 100644
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:36.27-49.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/flash@0,0: simple-bus unit address
format error, expected "0"
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:51.27-64.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/flash@1,0: simple-bus unit address
format error, expected "100000000"
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:66.26-71.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/cpld@3,0: simple-bus unit address format
error, expected "300000000"
Hi Rob,
I saw these warnings, but cannot find a good solution to it. The first cell in the address is the Chip select, while the second cell in the address is the address offset within the chip select. It would confusing to combine the two cells of different purposes into a single address as suggested by the warning. Can we allow the multi-cell address in the node name?
Regards,
Leo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Rob Herring <robh@kernel.org> Date: 2021-02-08 20:03:04
On Mon, Feb 08, 2021 at 05:07:14PM +0000, Leo Li wrote:
quoted
-----Original Message-----
From: Rob Herring <robh@kernel.org>
Sent: Monday, February 8, 2021 10:55 AM
To: Leo Li <redacted>
Cc: linux-arm-kernel@lists.infradead.org; Oleksij Rempel <linux@rempel-
privat.de>; Rob Herring [off-list ref]; Krzysztof Kozlowski
[off-list ref]; devicetree@vger.kernel.org; linux-
kernel@vger.kernel.org; Shawn Guo [off-list ref]
Subject: Re: [PATCH 03/15] dt-bindings: memory: fsl: convert ifc binding to
yaml schema
On Fri, 05 Feb 2021 17:47:22 -0600, Li Yang wrote:
quoted
Convert the txt binding to yaml format and add description. Also
updated the recommended node name to ifc-bus to align with the
simple-bus node name requirements.
Signed-off-by: Li Yang <redacted>
---
.../bindings/memory-controllers/fsl/ifc.txt | 82 ----------
.../bindings/memory-controllers/fsl/ifc.yaml | 140
++++++++++++++++++
2 files changed, 140 insertions(+), 82 deletions(-) delete mode
100644
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
create mode 100644
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:36.27-49.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/flash@0,0: simple-bus unit address
format error, expected "0"
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:51.27-64.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/flash@1,0: simple-bus unit address
format error, expected "100000000"
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:66.26-71.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/cpld@3,0: simple-bus unit address format
error, expected "300000000"
Hi Rob,
I saw these warnings, but cannot find a good solution to it. The
first cell in the address is the Chip select, while the second cell
in the address is the address offset within the chip select. It
would confusing to combine the two cells of different purposes into
a single address as suggested by the warning. Can we allow the
multi-cell address in the node name?
Drop 'simple-bus'. It's not a simple bus. You have registers that
presumably have some configuration needed.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
-----Original Message-----
From: Rob Herring <robh@kernel.org>
Sent: Monday, February 8, 2021 12:21 PM
To: Leo Li <redacted>
Cc: linux-arm-kernel@lists.infradead.org; Oleksij Rempel <linux@rempel-
privat.de>; Krzysztof Kozlowski [off-list ref];
devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Shawn Guo
[off-list ref]
Subject: Re: [PATCH 03/15] dt-bindings: memory: fsl: convert ifc binding to
yaml schema
On Mon, Feb 08, 2021 at 05:07:14PM +0000, Leo Li wrote:
quoted
quoted
-----Original Message-----
From: Rob Herring <robh@kernel.org>
Sent: Monday, February 8, 2021 10:55 AM
To: Leo Li <redacted>
Cc: linux-arm-kernel@lists.infradead.org; Oleksij Rempel
<linux@rempel- privat.de>; Rob Herring [off-list ref];
Krzysztof Kozlowski [off-list ref]; devicetree@vger.kernel.org;
linux- kernel@vger.kernel.org; Shawn Guo [off-list ref]
Subject: Re: [PATCH 03/15] dt-bindings: memory: fsl: convert ifc
binding to yaml schema
On Fri, 05 Feb 2021 17:47:22 -0600, Li Yang wrote:
quoted
Convert the txt binding to yaml format and add description. Also
updated the recommended node name to ifc-bus to align with the
simple-bus node name requirements.
Signed-off-by: Li Yang <redacted>
---
.../bindings/memory-controllers/fsl/ifc.txt | 82 ----------
.../bindings/memory-controllers/fsl/ifc.yaml | 140
++++++++++++++++++
2 files changed, 140 insertions(+), 82 deletions(-) delete mode
100644
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
create mode 100644
Documentation/devicetree/bindings/memory-controllers/fsl/ifc.yaml
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:36.27-49.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/flash@0,0: simple-bus unit address
format error, expected "0"
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:51.27-64.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/flash@1,0: simple-bus unit address
format error, expected "100000000"
Documentation/devicetree/bindings/memory-
controllers/fsl/ifc.example.dts:66.26-71.19: Warning (simple_bus_reg):
/example-0/soc/ifc-bus@ffe1e000/cpld@3,0: simple-bus unit address
format error, expected "300000000"
Hi Rob,
I saw these warnings, but cannot find a good solution to it. The
first cell in the address is the Chip select, while the second cell in
the address is the address offset within the chip select. It would
confusing to combine the two cells of different purposes into a single
address as suggested by the warning. Can we allow the multi-cell
address in the node name?
Drop 'simple-bus'. It's not a simple bus. You have registers that presumably
have some configuration needed.
That's probably true for just using "simple-bus" as compatible along. But I see many of the current bindings are defining a more specific compatible string in addition to the "simple-bus" compatible and have their own drivers. I think this probably meet the statement in the device tree spec? "Bindings may be defined as extensions of other each. For example a new bus type could be defined as an extension of the
simple-bus binding."
Regards,
Leo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Rob Herring <robh@kernel.org> Date: 2021-02-11 00:03:53
On Fri, 05 Feb 2021 17:47:20 -0600, Li Yang wrote:
Add the missing board in the binding docuemnt.
Signed-off-by: Li Yang <redacted>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)