There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz. Here add a new compatible
for MT8195, it's also supported in driver. But the first controller
(IP0) has no such issue, we prefer to use generic compatible,
e.g. mt8192's compatible.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 +
1 file changed, 1 insertion(+)
@@ -16,6 +16,7 @@ Required properties: "mediatek,mtk-xhci" compatible string, you need SoC specific ones in addition, one of: - "mediatek,mt8173-xhci"+ - "mediatek,mt8195-xhci" - reg : specifies physical base address and size of the registers - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control - interrupts : interrupt used by the controller
--
2.18.0
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There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz for those controllers.
Note: the first controller no need set it.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: fix typo of comaptible
---
drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
Add USB nodes, PHY nodes and some fixed regulator nodes.
We prefer to use mt8192's compatible for the first USB controller
(port0), there is no wrong with the SOF/ITP interval; but for other
controllers (port1~port3) should use mt8195's one due to the wrong
default setting of SOF/ITP interval which should be calculated from
48M, but not 24M by default.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 70 +++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 163 ++++++++++++++++++++
2 files changed, 233 insertions(+)
On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz. Here add a new compatible
for MT8195, it's also supported in driver. But the first controller
(IP0) has no such issue, we prefer to use generic compatible,
e.g. mt8192's compatible.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
Note, I do not apply patches with "RFC" as obviously you do not think
they are worthy of being applied. I don't see what you are asking to be
done with this set of patches, please explain?
thanks,
greg k-h
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On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz. Here add a new compatible
for MT8195, it's also supported in driver. But the first controller
(IP0) has no such issue, we prefer to use generic compatible,
e.g. mt8192's compatible.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
Note, I do not apply patches that have "RFC" as that means you do not
feel comfortable with them being applied.
Please resend without that when you feel they are ready to be merged.
thanks,
greg k-h
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On Wed, 2021-02-03 at 11:31 +0100, Greg Kroah-Hartman wrote:
On Wed, Feb 03, 2021 at 06:26:40PM +0800, Chunfeng Yun wrote:
quoted
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz. Here add a new compatible
for MT8195, it's also supported in driver. But the first controller
(IP0) has no such issue, we prefer to use generic compatible,
e.g. mt8192's compatible.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
Note, I do not apply patches with "RFC" as obviously you do not think
they are worthy of being applied. I don't see what you are asking to be
done with this set of patches, please explain?
The DTS patch [2/3] in the series will cause merge conflict, due to the
dependent patches are not upstreamed.
Another problem is that I wander to know whether the compatible usage as
following is allowed:
arch/arm64/boot/dts/mediatek/mt8195.dtsi
usb@11200000 { // ip0
compatible = "mediatek,mt8192-xhci", // here use mt8192's
compatible, avoid changing SOF/ITP interval for ip0, because it's
default value is ok."mediatek,mt8192-xhci" is not supported in driver,
so finally will use generic copatible "mediatek,mtk-xhci".
"mediatek,mtk-xhci";
....
};
usb@11290000 { // ip1
compatible = "mediatek,mt8195-xhci", // here use mt8195's
compatible, used to change SOF/ITP interval, due the the wrong default
value.
"mediatek,mtk-xhci";
};
usb@112a0000 { // ip2
compatible = "mediatek,mt8195-xhci", // same as ip1
"mediatek,mtk-xhci";
};
Thank you
Hi Mathias,
On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote:
quoted hunk
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz for those controllers.
Note: the first controller no need set it.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: fix typo of comaptible
---
drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
Can I Read/Write the following xHCI controller's registers in
xhci-mtk.c?
Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a
glue driver used to initialize clocks/power and IPPC registers which
don't belong to xHCI controller.
Thanks
quoted hunk
+/* xHCI csr */
+#define LS_EOF 0x930
+#define LS_EOF_OFFSET 0x89
+
+#define FS_EOF 0x934
+#define FS_EOF_OFFSET 0x2e
+
+#define SS_GEN1_EOF 0x93c
+#define SS_GEN1_EOF_OFFSET 0x78
+
+#define HFCNTR_CFG 0x944
+#define ITP_DELTA_CLK (0xa << 1)
+#define ITP_DELTA_CLK_MASK GENMASK(5, 1)
+#define FRMCNT_LEV1_RANG (0x12b << 8)
+#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
+
+#define SS_GEN2_EOF 0x990
+#define SS_GEN2_EOF_OFFSET 0x3c
+#define EOF_OFFSET_MASK GENMASK(11, 0)
+
enum ssusb_uwk_vers {
SSUSB_UWK_V1 = 1,
SSUSB_UWK_V2,
};
+/*
+ * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
+ * is calculated from the frame counter clock 24M, but in fact, the clock
+ * is 48M, so need change the interval.
+ */
+static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
+{
+ struct device *dev = mtk->dev;
+ struct usb_hcd *hcd = mtk->hcd;
+ u32 value;
+
+ if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
+ return;
+
+ value = readl(hcd->regs + HFCNTR_CFG);
+ value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
+ value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
+ writel(value, hcd->regs + HFCNTR_CFG);
+
+ value = readl(hcd->regs + LS_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= LS_EOF_OFFSET;
+ writel(value, hcd->regs + LS_EOF);
+
+ value = readl(hcd->regs + FS_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= FS_EOF_OFFSET;
+ writel(value, hcd->regs + FS_EOF);
+
+ value = readl(hcd->regs + SS_GEN1_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= SS_GEN1_EOF_OFFSET;
+ writel(value, hcd->regs + SS_GEN1_EOF);
+
+ value = readl(hcd->regs + SS_GEN2_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= SS_GEN2_EOF_OFFSET;
+ writel(value, hcd->regs + SS_GEN2_EOF);
+}
+
static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
{
struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
@@ -407,6 +467,8 @@ static int xhci_mtk_setup(struct usb_hcd *hcd) ret = xhci_mtk_ssusb_config(mtk); if (ret) return ret;++ xhci_mtk_set_frame_interval(mtk); } ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
Hi Mathias,
On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote:
quoted
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz for those controllers.
Note: the first controller no need set it.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: fix typo of comaptible
---
drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
Can I Read/Write the following xHCI controller's registers in
xhci-mtk.c?
Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a
glue driver used to initialize clocks/power and IPPC registers which
don't belong to xHCI controller.
These *_EOF registers look like they are Mediatek vendor specific registers
and not part of public xHCI register-level spec.
So I think accessing them from xhci-mtk.c makes sense.
If those register offsets are hardcoded like this in the Mediatek spec then
this is fine, but if those offsets are found from a vendor specific xHCI
extended capability entry (see xhci spec section 7) then we should dig them out
from there.
quoted
+/* xHCI csr */
+#define LS_EOF 0x930
+#define LS_EOF_OFFSET 0x89
+
+#define FS_EOF 0x934
+#define FS_EOF_OFFSET 0x2e
+
+#define SS_GEN1_EOF 0x93c
+#define SS_GEN1_EOF_OFFSET 0x78
+
+#define HFCNTR_CFG 0x944
+#define ITP_DELTA_CLK (0xa << 1)
+#define ITP_DELTA_CLK_MASK GENMASK(5, 1)
+#define FRMCNT_LEV1_RANG (0x12b << 8)
+#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
+
+#define SS_GEN2_EOF 0x990
+#define SS_GEN2_EOF_OFFSET 0x3c
+#define EOF_OFFSET_MASK GENMASK(11, 0)
+
enum ssusb_uwk_vers {
SSUSB_UWK_V1 = 1,
SSUSB_UWK_V2,
};
+/*
+ * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
+ * is calculated from the frame counter clock 24M, but in fact, the clock
+ * is 48M, so need change the interval.
+ */
+static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
+{
+ struct device *dev = mtk->dev;
+ struct usb_hcd *hcd = mtk->hcd;
+ u32 value;
+
+ if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
+ return;
+
+ value = readl(hcd->regs + HFCNTR_CFG);
+ value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
+ value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
+ writel(value, hcd->regs + HFCNTR_CFG);
+
+ value = readl(hcd->regs + LS_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= LS_EOF_OFFSET;
+ writel(value, hcd->regs + LS_EOF);
+
+ value = readl(hcd->regs + FS_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= FS_EOF_OFFSET;
+ writel(value, hcd->regs + FS_EOF);
+
+ value = readl(hcd->regs + SS_GEN1_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= SS_GEN1_EOF_OFFSET;
+ writel(value, hcd->regs + SS_GEN1_EOF);
+
+ value = readl(hcd->regs + SS_GEN2_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= SS_GEN2_EOF_OFFSET;
+ writel(value, hcd->regs + SS_GEN2_EOF);
Minor nit about names,
Register offsets from MMIO start are named *_EOF while clock multipliers? are named *_EOF_OFFSET.
This was a bit confusing
Thanks
-Mathias
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From: Rob Herring <robh@kernel.org> Date: 2021-02-10 21:59:55
On Wed, 03 Feb 2021 18:26:40 +0800, Chunfeng Yun wrote:
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz. Here add a new compatible
for MT8195, it's also supported in driver. But the first controller
(IP0) has no such issue, we prefer to use generic compatible,
e.g. mt8192's compatible.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: no changes
---
Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 +
1 file changed, 1 insertion(+)
On Mon, 2021-02-08 at 13:43 +0200, Mathias Nyman wrote:
On 7.2.2021 4.27, Chunfeng Yun wrote:
quoted
Hi Mathias,
On Wed, 2021-02-03 at 18:26 +0800, Chunfeng Yun wrote:
quoted
There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we should set
the accurate interval according to 48Mhz for those controllers.
Note: the first controller no need set it.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2: fix typo of comaptible
---
drivers/usb/host/xhci-mtk.c | 63 +++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
Can I Read/Write the following xHCI controller's registers in
xhci-mtk.c?
Ideally, xhci-mtk.c should not access them, because xhci-mtk is only a
glue driver used to initialize clocks/power and IPPC registers which
don't belong to xHCI controller.
These *_EOF registers look like they are Mediatek vendor specific registers
and not part of public xHCI register-level spec.
So I think accessing them from xhci-mtk.c makes sense.
If those register offsets are hardcoded like this in the Mediatek spec then
this is fine,
Check it with our DE, it's this case.
but if those offsets are found from a vendor specific xHCI
extended capability entry (see xhci spec section 7) then we should dig them out
from there.
quoted
quoted
+/* xHCI csr */
+#define LS_EOF 0x930
+#define LS_EOF_OFFSET 0x89
+
+#define FS_EOF 0x934
+#define FS_EOF_OFFSET 0x2e
+
+#define SS_GEN1_EOF 0x93c
+#define SS_GEN1_EOF_OFFSET 0x78
+
+#define HFCNTR_CFG 0x944
+#define ITP_DELTA_CLK (0xa << 1)
+#define ITP_DELTA_CLK_MASK GENMASK(5, 1)
+#define FRMCNT_LEV1_RANG (0x12b << 8)
+#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
+
+#define SS_GEN2_EOF 0x990
+#define SS_GEN2_EOF_OFFSET 0x3c
+#define EOF_OFFSET_MASK GENMASK(11, 0)
+
enum ssusb_uwk_vers {
SSUSB_UWK_V1 = 1,
SSUSB_UWK_V2,
};
+/*
+ * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
+ * is calculated from the frame counter clock 24M, but in fact, the clock
+ * is 48M, so need change the interval.
+ */
+static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
+{
+ struct device *dev = mtk->dev;
+ struct usb_hcd *hcd = mtk->hcd;
+ u32 value;
+
+ if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
+ return;
+
+ value = readl(hcd->regs + HFCNTR_CFG);
+ value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
+ value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
+ writel(value, hcd->regs + HFCNTR_CFG);
+
+ value = readl(hcd->regs + LS_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= LS_EOF_OFFSET;
+ writel(value, hcd->regs + LS_EOF);
+
+ value = readl(hcd->regs + FS_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= FS_EOF_OFFSET;
+ writel(value, hcd->regs + FS_EOF);
+
+ value = readl(hcd->regs + SS_GEN1_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= SS_GEN1_EOF_OFFSET;
+ writel(value, hcd->regs + SS_GEN1_EOF);
+
+ value = readl(hcd->regs + SS_GEN2_EOF);
+ value &= ~EOF_OFFSET_MASK;
+ value |= SS_GEN2_EOF_OFFSET;
+ writel(value, hcd->regs + SS_GEN2_EOF);
Minor nit about names,
Register offsets from MMIO start are named *_EOF while clock multipliers? are named *_EOF_OFFSET.
This was a bit confusing
Good point, the names come from register map docs, I'll modify it,
thanks a lot