From: Marek Vasut <marex@denx.de> Date: 2021-01-06 20:46:03
Add another mux option for ethernet0 pins, this is used on DHCOM when
the ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin and
then fed back via PA1 pin.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <redacted>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <redacted>
Cc: Patrick Delaunay <redacted>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
From: Marek Vasut <marex@denx.de> Date: 2021-01-06 20:46:05
Add pinmux option for MCO2 pin. This is used on DHCOM when the
ethernet PHY 50 MHz clock is generated by the MCO2 on PG2 pin.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <redacted>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <redacted>
Cc: Patrick Delaunay <redacted>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
From: Marek Vasut <marex@denx.de> Date: 2021-01-06 20:46:08
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently does not
permit selecting the clock input from SoC pad. To make things worse, the
implementation of this is partly present and is split between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is incorrect.
First, the ETHRX clock in clk-stm32mp1.c only represents the ETHRXEN gate,
however it should represent also ETH_REF_CLK_SEL mux. The problem is that
the ETH_REF_CLK_SEL mux is currently configured in the DWMAC4 driver and
the ETH_REF_CLK_SEL bit is part of SYSCFG block, not the DWMAC4 or the
clock block.
Second, the ETHRX parent clock is either eth_clk_fb (ETHCK_K) or external
ETH_RX_CLK/ETH_REF_CLK_SEL, it is never CK_AXI.
This patch attempts to address the clock selection by adding fixed factor
clock to DT, which allows the user to select its upstream clock.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <redacted>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <redacted>
Cc: Patrick Delaunay <redacted>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
arch/arm/boot/dts/stm32mp151.dtsi | 8 ++++++++
drivers/clk/clk-stm32mp1.c | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
From: Marek Vasut <marex@denx.de> Date: 2021-01-06 20:46:11
Using the MCO2 output for the LAN8710i PHY clock and feedback clock
into the DWMAC reduces EMI, switch to MCO2.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <redacted>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <redacted>
Cc: Patrick Delaunay <redacted>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently does not
permit selecting the clock input from SoC pad. To make things worse, the
implementation of this is partly present and is split between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is incorrect.
Sorry but I don't understand which configuration is missing. I think we
can handle all possible cases for RMII. At the glue layer
(dwmac-stm32.c) clocks gates and syscfg are set regarding device tree
binding (see the tab in dwmac-stm32.c). You could have a look here for
more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency if you
want to select this path. Our current "clock tree" is done to fit with
our ST reference boards (we have more peripherals than PLL outputs so we
have to make choices). So yes for customer/partners boards this clock
tree has to be modified to better fit with the need (either using
assigned-clock-parent or by modifying bootloader clock tree (tf-a or
u-boot)).
First, the ETHRX clock in clk-stm32mp1.c only represents the ETHRXEN gate,
however it should represent also ETH_REF_CLK_SEL mux. The problem is that
the ETH_REF_CLK_SEL mux is currently configured in the DWMAC4 driver and
the ETH_REF_CLK_SEL bit is part of SYSCFG block, not the DWMAC4 or the
clock block.
dwmac4-stm32 doesn't contain code for dwmac4 but it contains the glue
around the dwmac4: syscfg, clocks ...
Second, the ETHRX parent clock is either eth_clk_fb (ETHCK_K) or external
ETH_RX_CLK/ETH_REF_CLK_SEL, it is never CK_AXI.
Why CK_AXI ?
Regards
Alex
quoted hunk
This patch attempts to address the clock selection by adding fixed factor
clock to DT, which allows the user to select its upstream clock.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <redacted>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <redacted>
Cc: Patrick Delaunay <redacted>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
---
arch/arm/boot/dts/stm32mp151.dtsi | 8 ++++++++
drivers/clk/clk-stm32mp1.c | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
From: Marek Vasut <marex@denx.de> Date: 2021-01-15 12:18:01
On 1/14/21 6:08 PM, Alexandre TORGUE wrote:
Hi Marek
Hi,
On 1/6/21 9:43 PM, Marek Vasut wrote:
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently does not
permit selecting the clock input from SoC pad. To make things worse, the
implementation of this is partly present and is split between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is incorrect.
Sorry but I don't understand which configuration is missing. I think we
can handle all possible cases for RMII. At the glue layer
(dwmac-stm32.c) clocks gates and syscfg are set regarding device tree
binding (see the tab in dwmac-stm32.c). You could have a look here for
more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency if you
want to select this path. Our current "clock tree" is done to fit with
our ST reference boards (we have more peripherals than PLL outputs so we
have to make choices). So yes for customer/partners boards this clock
tree has to be modified to better fit with the need (either using
assigned-clock-parent or by modifying bootloader clock tree (tf-a or
u-boot)).
I don't think you handle all the configuration options, but I might also
be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the MP1
datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive the PHY
clock, and uses eth_clk_fb to supply ETH_RX_CLK. However, the 50 MHz is
sourced directly from PLL4P, which then has to run at 50 MHz and that in
turn reduces clock frequency for other blocks connected to PLL4P (e.g.
SDMMC, where the impact is noticable).
So, what I want to model here is this:
PLL4P = 100 MHz
MCO2 is supplied by PLL4P and set to /2 , so MCO2 = 50 MHz
SoC pad PG2 is set as MCO2 output, thus a source of 50 MHz signal
SoC pad PA1 is set as ETH_RX_CLK and connected to PG2
This works fine in practice, except it cannot be modeled using current
DT bindings, even though it should be possible to model it.
quoted
First, the ETHRX clock in clk-stm32mp1.c only represents the ETHRXEN
gate,
however it should represent also ETH_REF_CLK_SEL mux. The problem is that
the ETH_REF_CLK_SEL mux is currently configured in the DWMAC4 driver and
the ETH_REF_CLK_SEL bit is part of SYSCFG block, not the DWMAC4 or the
clock block.
dwmac4-stm32 doesn't contain code for dwmac4 but it contains the glue
around the dwmac4: syscfg, clocks ...
The problem is that dwmac4-stm32 isn't the right place to configure the
ETHRX clock mux, that should be in the clock driver. So the stm32 clock
driver should have SYSCFG handle and configure ETH_REF_CLK_SEL mux. The
"st,eth-ref-clk-sel" DT prop would then not be needed at all, as the
reference clock select would be configured using assigned-clocks in DT.
The default assigned-clocks should be eth_clk_fb , but the user can
override it in the DT and provide another clock source (e.g. in my case,
that would be PLL4P->MCO2->ETHRX).
quoted
Second, the ETHRX parent clock is either eth_clk_fb (ETHCK_K) or external
ETH_RX_CLK/ETH_REF_CLK_SEL, it is never CK_AXI.
Why CK_AXI ?
See drivers/clk/clk-stm32mp1.c:
1895 PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
[...]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently does not
permit selecting the clock input from SoC pad. To make things worse, the
implementation of this is partly present and is split between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is incorrect.
Sorry but I don't understand which configuration is missing. I think
we can handle all possible cases for RMII. At the glue layer
(dwmac-stm32.c) clocks gates and syscfg are set regarding device tree
binding (see the tab in dwmac-stm32.c). You could have a look here for
more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency if you
want to select this path. Our current "clock tree" is done to fit with
our ST reference boards (we have more peripherals than PLL outputs so
we have to make choices). So yes for customer/partners boards this
clock tree has to be modified to better fit with the need (either
using assigned-clock-parent or by modifying bootloader clock tree
(tf-a or u-boot)).
I don't think you handle all the configuration options, but I might also
be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the MP1
datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive the PHY
clock, and uses eth_clk_fb to supply ETH_RX_CLK. However, the 50 MHz is
sourced directly from PLL4P, which then has to run at 50 MHz and that in
turn reduces clock frequency for other blocks connected to PLL4P (e.g.
SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using the
ref_clk coming from the PHY. And yes I can understand that the drawback
is huge).
So, what I want to model here is this:
PLL4P = 100 MHz
MCO2 is supplied by PLL4P and set to /2 , so MCO2 = 50 MHz
SoC pad PG2 is set as MCO2 output, thus a source of 50 MHz signal
SoC pad PA1 is set as ETH_RX_CLK and connected to PG2
Ok I see (to be honest IIWR we didn't test i :$) but it should work.
This works fine in practice, except it cannot be modeled using current
DT bindings, even though it should be possible to model it.
For dwmac point of view it's quite the same thing to have your PHY
clocking by MCO or by a crystal. You just need to configure RX_REF pad
and ETH_CLK_SEL to get the 50 MHz RMII reference clock.
quoted
quoted
First, the ETHRX clock in clk-stm32mp1.c only represents the ETHRXEN
gate,
however it should represent also ETH_REF_CLK_SEL mux. The problem is
that
the ETH_REF_CLK_SEL mux is currently configured in the DWMAC4 driver and
the ETH_REF_CLK_SEL bit is part of SYSCFG block, not the DWMAC4 or the
clock block.
dwmac4-stm32 doesn't contain code for dwmac4 but it contains the glue
around the dwmac4: syscfg, clocks ...
The problem is that dwmac4-stm32 isn't the right place to configure the
ETHRX clock mux, that should be in the clock driver. So the stm32 clock
driver should have SYSCFG handle and configure ETH_REF_CLK_SEL mux. The
"st,eth-ref-clk-sel" DT prop would then not be needed at all, as the
reference clock select would be configured using assigned-clocks in DT.
Idea was to keep at the same place the Ethernet glue configuration. We
can't move all this glue into clock driver as phy interface is needed to
well configure some sysconf registers. Current dwamc-stm32 glue is
working and documented. I'm not convinced to develop a new one by
splitting clock sysconf in clock driver and phy interface management at
ethernet level. I think we will get the same functional result (but yes
maybe more understandable at dt-bindings level). We could maybe update
binding name to be more clear.
The default assigned-clocks should be eth_clk_fb , but the user can
override it in the DT and provide another clock source (e.g. in my case,
that would be PLL4P->MCO2->ETHRX).
quoted
quoted
Second, the ETHRX parent clock is either eth_clk_fb (ETHCK_K) or
external
ETH_RX_CLK/ETH_REF_CLK_SEL, it is never CK_AXI.
Why CK_AXI ?
See drivers/clk/clk-stm32mp1.c:
1895 PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
Ok I see, and it is the same case for TX also. Discussing with our clock
expert it was done for simplification.
regards
Alex
From: Marek Vasut <marex@denx.de> Date: 2021-01-16 17:03:39
On 1/15/21 4:22 PM, Alexandre TORGUE wrote:
Hi,
[...]
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently does
not
permit selecting the clock input from SoC pad. To make things worse,
the
implementation of this is partly present and is split between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is
incorrect.
Sorry but I don't understand which configuration is missing. I think
we can handle all possible cases for RMII. At the glue layer
(dwmac-stm32.c) clocks gates and syscfg are set regarding device tree
binding (see the tab in dwmac-stm32.c). You could have a look here
for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency if
you want to select this path. Our current "clock tree" is done to fit
with our ST reference boards (we have more peripherals than PLL
outputs so we have to make choices). So yes for customer/partners
boards this clock tree has to be modified to better fit with the need
(either using assigned-clock-parent or by modifying bootloader clock
tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but I might
also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the MP1
datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive the PHY
clock, and uses eth_clk_fb to supply ETH_RX_CLK. However, the 50 MHz
is sourced directly from PLL4P, which then has to run at 50 MHz and
that in turn reduces clock frequency for other blocks connected to
PLL4P (e.g. SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using the
ref_clk coming from the PHY. And yes I can understand that the drawback
is huge).
So lets fix it.
quoted
So, what I want to model here is this:
PLL4P = 100 MHz
MCO2 is supplied by PLL4P and set to /2 , so MCO2 = 50 MHz
SoC pad PG2 is set as MCO2 output, thus a source of 50 MHz signal
SoC pad PA1 is set as ETH_RX_CLK and connected to PG2
Ok I see (to be honest IIWR we didn't test i :$) but it should work.
It does work, I have boards which use this setup already.
quoted
This works fine in practice, except it cannot be modeled using current
DT bindings, even though it should be possible to model it.
For dwmac point of view it's quite the same thing to have your PHY
clocking by MCO or by a crystal. You just need to configure RX_REF pad
and ETH_CLK_SEL to get the 50 MHz RMII reference clock.
Yes
quoted
quoted
quoted
First, the ETHRX clock in clk-stm32mp1.c only represents the ETHRXEN
gate,
however it should represent also ETH_REF_CLK_SEL mux. The problem is
that
the ETH_REF_CLK_SEL mux is currently configured in the DWMAC4 driver
and
the ETH_REF_CLK_SEL bit is part of SYSCFG block, not the DWMAC4 or the
clock block.
dwmac4-stm32 doesn't contain code for dwmac4 but it contains the glue
around the dwmac4: syscfg, clocks ...
The problem is that dwmac4-stm32 isn't the right place to configure
the ETHRX clock mux, that should be in the clock driver. So the stm32
clock driver should have SYSCFG handle and configure ETH_REF_CLK_SEL
mux. The "st,eth-ref-clk-sel" DT prop would then not be needed at all,
as the reference clock select would be configured using
assigned-clocks in DT.
Idea was to keep at the same place the Ethernet glue configuration. We
can't move all this glue into clock driver as phy interface is needed to
well configure some sysconf registers.
This configuration can be done by the clock driver too. And in fact, I
believe it should be done by the clock driver, just like it's done for
all the other clock muxes with gates in the clock driver, except in this
case the mux is in syscfg and gate is in rcc.
Current dwamc-stm32 glue is
working and documented. I'm not convinced to develop a new one by
splitting clock sysconf in clock driver and phy interface management at
ethernet level. I think we will get the same functional result (but yes
maybe more understandable at dt-bindings level). We could maybe update
binding name to be more clear.
You don't get the same result, since you cannot model the MCO2 input
into ETHRX. Or can you ?
I also think that we won't need new binding altogether, just a slight
tweak to the existing ones which would permit modeling the MCO2 input
into ETHRX, I am open to suggestions how to do it. Note that the clock
framework must be able to turn off both ETHRX gate, MCO2 and all the way
up the tree if ETHRX is turned off.
quoted
The default assigned-clocks should be eth_clk_fb , but the user can
override it in the DT and provide another clock source (e.g. in my
case, that would be PLL4P->MCO2->ETHRX).
quoted
quoted
Second, the ETHRX parent clock is either eth_clk_fb (ETHCK_K) or
external
ETH_RX_CLK/ETH_REF_CLK_SEL, it is never CK_AXI.
Why CK_AXI ?
See drivers/clk/clk-stm32mp1.c:
1895 PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
Ok I see, and it is the same case for TX also. Discussing with our clock
expert it was done for simplification.
On 1/15/21 4:22 PM, Alexandre TORGUE wrote:
Hi,
[...]
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently
does not
permit selecting the clock input from SoC pad. To make things
worse, the
implementation of this is partly present and is split between the
clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is
incorrect.
Sorry but I don't understand which configuration is missing. I think
we can handle all possible cases for RMII. At the glue layer
(dwmac-stm32.c) clocks gates and syscfg are set regarding device
tree binding (see the tab in dwmac-stm32.c). You could have a look
here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency if
you want to select this path. Our current "clock tree" is done to
fit with our ST reference boards (we have more peripherals than PLL
outputs so we have to make choices). So yes for customer/partners
boards this clock tree has to be modified to better fit with the
need (either using assigned-clock-parent or by modifying bootloader
clock tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but I might
also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the MP1
datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive the PHY
clock, and uses eth_clk_fb to supply ETH_RX_CLK. However, the 50 MHz
is sourced directly from PLL4P, which then has to run at 50 MHz and
that in turn reduces clock frequency for other blocks connected to
PLL4P (e.g. SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using the
ref_clk coming from the PHY. And yes I can understand that the
drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration issue.
Either you don't use PLL4P for Ethernet (what you're doing) or you don't
use PLL4P for SDMMC. But yes, there are not a lot of possibilities.
quoted
quoted
So, what I want to model here is this:
PLL4P = 100 MHz
MCO2 is supplied by PLL4P and set to /2 , so MCO2 = 50 MHz
SoC pad PG2 is set as MCO2 output, thus a source of 50 MHz signal
SoC pad PA1 is set as ETH_RX_CLK and connected to PG2
Ok I see (to be honest IIWR we didn't test i :$) but it should work.
It does work, I have boards which use this setup already.
quoted
quoted
This works fine in practice, except it cannot be modeled using
current DT bindings, even though it should be possible to model it.
For dwmac point of view it's quite the same thing to have your PHY
clocking by MCO or by a crystal. You just need to configure RX_REF pad
and ETH_CLK_SEL to get the 50 MHz RMII reference clock.
Yes
quoted
quoted
quoted
quoted
First, the ETHRX clock in clk-stm32mp1.c only represents the
ETHRXEN gate,
however it should represent also ETH_REF_CLK_SEL mux. The problem
is that
the ETH_REF_CLK_SEL mux is currently configured in the DWMAC4
driver and
the ETH_REF_CLK_SEL bit is part of SYSCFG block, not the DWMAC4 or the
clock block.
dwmac4-stm32 doesn't contain code for dwmac4 but it contains the
glue around the dwmac4: syscfg, clocks ...
The problem is that dwmac4-stm32 isn't the right place to configure
the ETHRX clock mux, that should be in the clock driver. So the stm32
clock driver should have SYSCFG handle and configure ETH_REF_CLK_SEL
mux. The "st,eth-ref-clk-sel" DT prop would then not be needed at
all, as the reference clock select would be configured using
assigned-clocks in DT.
Idea was to keep at the same place the Ethernet glue configuration. We
can't move all this glue into clock driver as phy interface is needed
to well configure some sysconf registers.
This configuration can be done by the clock driver too. And in fact, I
believe it should be done by the clock driver, just like it's done for
all the other clock muxes with gates in the clock driver, except in this
case the mux is in syscfg and gate is in rcc.
As said, choice has been done to do it in dwmac-stm32, and sorry I see
more drawbacks than benefits to move it now.
quoted
Current dwamc-stm32 glue is working and documented. I'm not convinced
to develop a new one by splitting clock sysconf in clock driver and
phy interface management at ethernet level. I think we will get the
same functional result (but yes maybe more understandable at
dt-bindings level). We could maybe update binding name to be more clear.
You don't get the same result, since you cannot model the MCO2 input
into ETHRX. Or can you ?
Why do you want to model MCO2 into ETHRX ? MCO2 just replace a crystal,
and when a crystal is used, it is not modeled. I think is it the same
case for MCO2.
I also think that we won't need new binding altogether, just a slight
tweak to the existing ones which would permit modeling the MCO2 input
into ETHRX, I am open to suggestions how to do it. Note that the clock
framework must be able to turn off both ETHRX gate, MCO2 and all the way
up the tree if ETHRX is turned off.
quoted
quoted
The default assigned-clocks should be eth_clk_fb , but the user can
override it in the DT and provide another clock source (e.g. in my
case, that would be PLL4P->MCO2->ETHRX).
quoted
quoted
Second, the ETHRX parent clock is either eth_clk_fb (ETHCK_K) or
external
ETH_RX_CLK/ETH_REF_CLK_SEL, it is never CK_AXI.
Why CK_AXI ?
See drivers/clk/clk-stm32mp1.c:
1895 PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
Ok I see, and it is the same case for TX also. Discussing with our
clock expert it was done for simplification.
From: Marek Vasut <marex@denx.de> Date: 2021-01-26 10:42:25
On 1/26/21 11:17 AM, Alexandre TORGUE wrote:
On 1/16/21 6:01 PM, Marek Vasut wrote:
quoted
On 1/15/21 4:22 PM, Alexandre TORGUE wrote:
Hi,
[...]
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently
does not
permit selecting the clock input from SoC pad. To make things
worse, the
implementation of this is partly present and is split between the
clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is
incorrect.
Sorry but I don't understand which configuration is missing. I
think we can handle all possible cases for RMII. At the glue layer
(dwmac-stm32.c) clocks gates and syscfg are set regarding device
tree binding (see the tab in dwmac-stm32.c). You could have a look
here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency if
you want to select this path. Our current "clock tree" is done to
fit with our ST reference boards (we have more peripherals than PLL
outputs so we have to make choices). So yes for customer/partners
boards this clock tree has to be modified to better fit with the
need (either using assigned-clock-parent or by modifying bootloader
clock tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but I might
also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the MP1
datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive the
PHY clock, and uses eth_clk_fb to supply ETH_RX_CLK. However, the 50
MHz is sourced directly from PLL4P, which then has to run at 50 MHz
and that in turn reduces clock frequency for other blocks connected
to PLL4P (e.g. SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using the
ref_clk coming from the PHY. And yes I can understand that the
drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration issue.
Either you don't use PLL4P for Ethernet (what you're doing) or you don't
use PLL4P for SDMMC. But yes, there are not a lot of possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To enable
this entire chain of clock, I need the correct clock tree. Currently
that cannot be modeled, can it?
quoted
quoted
quoted
So, what I want to model here is this:
PLL4P = 100 MHz
MCO2 is supplied by PLL4P and set to /2 , so MCO2 = 50 MHz
SoC pad PG2 is set as MCO2 output, thus a source of 50 MHz signal
SoC pad PA1 is set as ETH_RX_CLK and connected to PG2
Ok I see (to be honest IIWR we didn't test i :$) but it should work.
It does work, I have boards which use this setup already.
quoted
quoted
This works fine in practice, except it cannot be modeled using
current DT bindings, even though it should be possible to model it.
For dwmac point of view it's quite the same thing to have your PHY
clocking by MCO or by a crystal. You just need to configure RX_REF
pad and ETH_CLK_SEL to get the 50 MHz RMII reference clock.
Yes
quoted
quoted
quoted
quoted
First, the ETHRX clock in clk-stm32mp1.c only represents the
ETHRXEN gate,
however it should represent also ETH_REF_CLK_SEL mux. The problem
is that
the ETH_REF_CLK_SEL mux is currently configured in the DWMAC4
driver and
the ETH_REF_CLK_SEL bit is part of SYSCFG block, not the DWMAC4 or
the
clock block.
dwmac4-stm32 doesn't contain code for dwmac4 but it contains the
glue around the dwmac4: syscfg, clocks ...
The problem is that dwmac4-stm32 isn't the right place to configure
the ETHRX clock mux, that should be in the clock driver. So the
stm32 clock driver should have SYSCFG handle and configure
ETH_REF_CLK_SEL mux. The "st,eth-ref-clk-sel" DT prop would then not
be needed at all, as the reference clock select would be configured
using assigned-clocks in DT.
Idea was to keep at the same place the Ethernet glue configuration.
We can't move all this glue into clock driver as phy interface is
needed to well configure some sysconf registers.
This configuration can be done by the clock driver too. And in fact, I
believe it should be done by the clock driver, just like it's done for
all the other clock muxes with gates in the clock driver, except in
this case the mux is in syscfg and gate is in rcc.
As said, choice has been done to do it in dwmac-stm32, and sorry I see
more drawbacks than benefits to move it now.
Surely a backward-compatible implementation would be possible, how do
you feel about that ?
quoted
quoted
Current dwamc-stm32 glue is working and documented. I'm not convinced
to develop a new one by splitting clock sysconf in clock driver and
phy interface management at ethernet level. I think we will get the
same functional result (but yes maybe more understandable at
dt-bindings level). We could maybe update binding name to be more clear.
You don't get the same result, since you cannot model the MCO2 input
into ETHRX. Or can you ?
Why do you want to model MCO2 into ETHRX ? MCO2 just replace a crystal,
and when a crystal is used, it is not modeled. I think is it the same
case for MCO2.
I need to correctly enable all the clock instead of keeping MCO2 enabled
all the time. If ethrx is not needed, the clock are disabled and if even
the upstream clock are no longer needed, they (MCO2, and then PLL4P) can
be disabled too.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 1/15/21 4:22 PM, Alexandre TORGUE wrote:
Hi,
[...]
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently
does not
permit selecting the clock input from SoC pad. To make things
worse, the
implementation of this is partly present and is split between the
clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is
incorrect.
Sorry but I don't understand which configuration is missing. I
think we can handle all possible cases for RMII. At the glue layer
(dwmac-stm32.c) clocks gates and syscfg are set regarding device
tree binding (see the tab in dwmac-stm32.c). You could have a look
here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency if
you want to select this path. Our current "clock tree" is done to
fit with our ST reference boards (we have more peripherals than
PLL outputs so we have to make choices). So yes for
customer/partners boards this clock tree has to be modified to
better fit with the need (either using assigned-clock-parent or by
modifying bootloader clock tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but I might
also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the
MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive the
PHY clock, and uses eth_clk_fb to supply ETH_RX_CLK. However, the
50 MHz is sourced directly from PLL4P, which then has to run at 50
MHz and that in turn reduces clock frequency for other blocks
connected to PLL4P (e.g. SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using the
ref_clk coming from the PHY. And yes I can understand that the
drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration issue.
Either you don't use PLL4P for Ethernet (what you're doing) or you
don't use PLL4P for SDMMC. But yes, there are not a lot of possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To enable
this entire chain of clock, I need the correct clock tree. Currently
that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide a clock
to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
quoted
quoted
quoted
quoted
So, what I want to model here is this:
PLL4P = 100 MHz
MCO2 is supplied by PLL4P and set to /2 , so MCO2 = 50 MHz
SoC pad PG2 is set as MCO2 output, thus a source of 50 MHz signal
SoC pad PA1 is set as ETH_RX_CLK and connected to PG2
Ok I see (to be honest IIWR we didn't test i :$) but it should work.
It does work, I have boards which use this setup already.
quoted
quoted
This works fine in practice, except it cannot be modeled using
current DT bindings, even though it should be possible to model it.
For dwmac point of view it's quite the same thing to have your PHY
clocking by MCO or by a crystal. You just need to configure RX_REF
pad and ETH_CLK_SEL to get the 50 MHz RMII reference clock.
Yes
quoted
quoted
quoted
quoted
First, the ETHRX clock in clk-stm32mp1.c only represents the
ETHRXEN gate,
however it should represent also ETH_REF_CLK_SEL mux. The problem
is that
the ETH_REF_CLK_SEL mux is currently configured in the DWMAC4
driver and
the ETH_REF_CLK_SEL bit is part of SYSCFG block, not the DWMAC4
or the
clock block.
dwmac4-stm32 doesn't contain code for dwmac4 but it contains the
glue around the dwmac4: syscfg, clocks ...
The problem is that dwmac4-stm32 isn't the right place to configure
the ETHRX clock mux, that should be in the clock driver. So the
stm32 clock driver should have SYSCFG handle and configure
ETH_REF_CLK_SEL mux. The "st,eth-ref-clk-sel" DT prop would then
not be needed at all, as the reference clock select would be
configured using assigned-clocks in DT.
Idea was to keep at the same place the Ethernet glue configuration.
We can't move all this glue into clock driver as phy interface is
needed to well configure some sysconf registers.
This configuration can be done by the clock driver too. And in fact,
I believe it should be done by the clock driver, just like it's done
for all the other clock muxes with gates in the clock driver, except
in this case the mux is in syscfg and gate is in rcc.
As said, choice has been done to do it in dwmac-stm32, and sorry I see
more drawbacks than benefits to move it now.
Surely a backward-compatible implementation would be possible, how do
you feel about that ?
Well done I can't say "no" in this case.
quoted
quoted
quoted
Current dwamc-stm32 glue is working and documented. I'm not
convinced to develop a new one by splitting clock sysconf in clock
driver and phy interface management at ethernet level. I think we
will get the same functional result (but yes maybe more
understandable at dt-bindings level). We could maybe update binding
name to be more clear.
You don't get the same result, since you cannot model the MCO2 input
into ETHRX. Or can you ?
Why do you want to model MCO2 into ETHRX ? MCO2 just replace a
crystal, and when a crystal is used, it is not modeled. I think is it
the same case for MCO2.
I need to correctly enable all the clock instead of keeping MCO2 enabled
all the time. If ethrx is not needed, the clock are disabled and if even
the upstream clock are no longer needed, they (MCO2, and then PLL4P) can
be disabled too.
From: Marek Vasut <marex@denx.de> Date: 2021-01-26 13:00:30
On 1/26/21 11:54 AM, Alexandre TORGUE wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently
does not
permit selecting the clock input from SoC pad. To make things
worse, the
implementation of this is partly present and is split between
the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is
incorrect.
Sorry but I don't understand which configuration is missing. I
think we can handle all possible cases for RMII. At the glue
layer (dwmac-stm32.c) clocks gates and syscfg are set regarding
device tree binding (see the tab in dwmac-stm32.c). You could
have a look here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency
if you want to select this path. Our current "clock tree" is done
to fit with our ST reference boards (we have more peripherals
than PLL outputs so we have to make choices). So yes for
customer/partners boards this clock tree has to be modified to
better fit with the need (either using assigned-clock-parent or
by modifying bootloader clock tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but I
might also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the
MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive the
PHY clock, and uses eth_clk_fb to supply ETH_RX_CLK. However, the
50 MHz is sourced directly from PLL4P, which then has to run at 50
MHz and that in turn reduces clock frequency for other blocks
connected to PLL4P (e.g. SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using the
ref_clk coming from the PHY. And yes I can understand that the
drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration issue.
Either you don't use PLL4P for Ethernet (what you're doing) or you
don't use PLL4P for SDMMC. But yes, there are not a lot of
possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To enable
this entire chain of clock, I need the correct clock tree. Currently
that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide a clock
to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
Because the X1 (MCO2 output) is the same net as 50 MHz ETH_REF_CLK
input. MCO2 output is routed on a SoC pin and that is connected with a
wire to ETH_REF_CLK SoC pin (input).
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 1/26/21 11:54 AM, Alexandre TORGUE wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling currently
does not
permit selecting the clock input from SoC pad. To make things
worse, the
implementation of this is partly present and is split between
the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is
incorrect.
Sorry but I don't understand which configuration is missing. I
think we can handle all possible cases for RMII. At the glue
layer (dwmac-stm32.c) clocks gates and syscfg are set regarding
device tree binding (see the tab in dwmac-stm32.c). You could
have a look here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency
if you want to select this path. Our current "clock tree" is
done to fit with our ST reference boards (we have more
peripherals than PLL outputs so we have to make choices). So yes
for customer/partners boards this clock tree has to be modified
to better fit with the need (either using assigned-clock-parent
or by modifying bootloader clock tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but I
might also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the
MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive the
PHY clock, and uses eth_clk_fb to supply ETH_RX_CLK. However, the
50 MHz is sourced directly from PLL4P, which then has to run at
50 MHz and that in turn reduces clock frequency for other blocks
connected to PLL4P (e.g. SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using the
ref_clk coming from the PHY. And yes I can understand that the
drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration
issue. Either you don't use PLL4P for Ethernet (what you're doing)
or you don't use PLL4P for SDMMC. But yes, there are not a lot of
possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To
enable this entire chain of clock, I need the correct clock tree.
Currently that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide a
clock to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
Because the X1 (MCO2 output) is the same net as 50 MHz ETH_REF_CLK
input. MCO2 output is routed on a SoC pin and that is connected with a
wire to ETH_REF_CLK SoC pin (input).
From: Marek Vasut <marex@denx.de> Date: 2021-01-26 15:44:05
On 1/26/21 4:40 PM, Alexandre TORGUE wrote:
On 1/26/21 1:59 PM, Marek Vasut wrote:
quoted
On 1/26/21 11:54 AM, Alexandre TORGUE wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling
currently does not
permit selecting the clock input from SoC pad. To make things
worse, the
implementation of this is partly present and is split between
the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is
incorrect.
Sorry but I don't understand which configuration is missing. I
think we can handle all possible cases for RMII. At the glue
layer (dwmac-stm32.c) clocks gates and syscfg are set regarding
device tree binding (see the tab in dwmac-stm32.c). You could
have a look here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well frequency
if you want to select this path. Our current "clock tree" is
done to fit with our ST reference boards (we have more
peripherals than PLL outputs so we have to make choices). So
yes for customer/partners boards this clock tree has to be
modified to better fit with the need (either using
assigned-clock-parent or by modifying bootloader clock tree
(tf-a or u-boot)).
I don't think you handle all the configuration options, but I
might also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in the
MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive
the PHY clock, and uses eth_clk_fb to supply ETH_RX_CLK.
However, the 50 MHz is sourced directly from PLL4P, which then
has to run at 50 MHz and that in turn reduces clock frequency
for other blocks connected to PLL4P (e.g. SDMMC, where the
impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using
the ref_clk coming from the PHY. And yes I can understand that
the drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration
issue. Either you don't use PLL4P for Ethernet (what you're doing)
or you don't use PLL4P for SDMMC. But yes, there are not a lot of
possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To
enable this entire chain of clock, I need the correct clock tree.
Currently that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide a
clock to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
Because the X1 (MCO2 output) is the same net as 50 MHz ETH_REF_CLK
input. MCO2 output is routed on a SoC pin and that is connected with a
wire to ETH_REF_CLK SoC pin (input).
Ok I see, but I don't think you have to link both clocks.
If I don't, then MCO2 will not have any consumer and would be turned off
by the kernel.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 1/26/21 11:54 AM, Alexandre TORGUE wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling
currently does not
permit selecting the clock input from SoC pad. To make things
worse, the
implementation of this is partly present and is split between
the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent is
incorrect.
Sorry but I don't understand which configuration is missing. I
think we can handle all possible cases for RMII. At the glue
layer (dwmac-stm32.c) clocks gates and syscfg are set
regarding device tree binding (see the tab in dwmac-stm32.c).
You could have a look here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well
frequency if you want to select this path. Our current "clock
tree" is done to fit with our ST reference boards (we have
more peripherals than PLL outputs so we have to make choices).
So yes for customer/partners boards this clock tree has to be
modified to better fit with the need (either using
assigned-clock-parent or by modifying bootloader clock tree
(tf-a or u-boot)).
I don't think you handle all the configuration options, but I
might also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in
the MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive
the PHY clock, and uses eth_clk_fb to supply ETH_RX_CLK.
However, the 50 MHz is sourced directly from PLL4P, which then
has to run at 50 MHz and that in turn reduces clock frequency
for other blocks connected to PLL4P (e.g. SDMMC, where the
impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using
the ref_clk coming from the PHY. And yes I can understand that
the drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration
issue. Either you don't use PLL4P for Ethernet (what you're doing)
or you don't use PLL4P for SDMMC. But yes, there are not a lot of
possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To
enable this entire chain of clock, I need the correct clock tree.
Currently that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide a
clock to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
Because the X1 (MCO2 output) is the same net as 50 MHz ETH_REF_CLK
input. MCO2 output is routed on a SoC pin and that is connected with
a wire to ETH_REF_CLK SoC pin (input).
Ok I see, but I don't think you have to link both clocks.
If I don't, then MCO2 will not have any consumer and would be turned off
by the kernel.
I agree, but IMO the MCO clock should be declared with CLK_IGNORE_UNUSED
flag in stm32mp1 clock driver.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
From: Marek Vasut <marex@denx.de> Date: 2021-01-26 19:13:33
On 1/26/21 5:47 PM, Alexandre TORGUE wrote:
On 1/26/21 4:42 PM, Marek Vasut wrote:
quoted
On 1/26/21 4:40 PM, Alexandre TORGUE wrote:
quoted
On 1/26/21 1:59 PM, Marek Vasut wrote:
quoted
On 1/26/21 11:54 AM, Alexandre TORGUE wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling
currently does not
permit selecting the clock input from SoC pad. To make
things worse, the
implementation of this is partly present and is split
between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent
is incorrect.
Sorry but I don't understand which configuration is missing.
I think we can handle all possible cases for RMII. At the
glue layer (dwmac-stm32.c) clocks gates and syscfg are set
regarding device tree binding (see the tab in dwmac-stm32.c).
You could have a look here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well
frequency if you want to select this path. Our current "clock
tree" is done to fit with our ST reference boards (we have
more peripherals than PLL outputs so we have to make
choices). So yes for customer/partners boards this clock tree
has to be modified to better fit with the need (either using
assigned-clock-parent or by modifying bootloader clock tree
(tf-a or u-boot)).
I don't think you handle all the configuration options, but I
might also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in
the MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive
the PHY clock, and uses eth_clk_fb to supply ETH_RX_CLK.
However, the 50 MHz is sourced directly from PLL4P, which then
has to run at 50 MHz and that in turn reduces clock frequency
for other blocks connected to PLL4P (e.g. SDMMC, where the
impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using
the ref_clk coming from the PHY. And yes I can understand that
the drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration
issue. Either you don't use PLL4P for Ethernet (what you're
doing) or you don't use PLL4P for SDMMC. But yes, there are not a
lot of possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To
enable this entire chain of clock, I need the correct clock tree.
Currently that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide a
clock to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
Because the X1 (MCO2 output) is the same net as 50 MHz ETH_REF_CLK
input. MCO2 output is routed on a SoC pin and that is connected with
a wire to ETH_REF_CLK SoC pin (input).
Ok I see, but I don't think you have to link both clocks.
If I don't, then MCO2 will not have any consumer and would be turned
off by the kernel.
I agree, but IMO the MCO clock should be declared with CLK_IGNORE_UNUSED
flag in stm32mp1 clock driver.
Why? It can be safely turned off if it is only used to supply ETHRX. And
if the clock tree is correctly modeled, that is what happens.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 1/26/21 11:54 AM, Alexandre TORGUE wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling
currently does not
permit selecting the clock input from SoC pad. To make
things worse, the
implementation of this is partly present and is split
between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent
is incorrect.
Sorry but I don't understand which configuration is missing.
I think we can handle all possible cases for RMII. At the
glue layer (dwmac-stm32.c) clocks gates and syscfg are set
regarding device tree binding (see the tab in
dwmac-stm32.c). You could have a look here for more details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well
frequency if you want to select this path. Our current
"clock tree" is done to fit with our ST reference boards (we
have more peripherals than PLL outputs so we have to make
choices). So yes for customer/partners boards this clock
tree has to be modified to better fit with the need (either
using assigned-clock-parent or by modifying bootloader clock
tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but I
might also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in
the MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to drive
the PHY clock, and uses eth_clk_fb to supply ETH_RX_CLK.
However, the 50 MHz is sourced directly from PLL4P, which
then has to run at 50 MHz and that in turn reduces clock
frequency for other blocks connected to PLL4P (e.g. SDMMC,
where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without using
the ref_clk coming from the PHY. And yes I can understand that
the drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration
issue. Either you don't use PLL4P for Ethernet (what you're
doing) or you don't use PLL4P for SDMMC. But yes, there are not
a lot of possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To
enable this entire chain of clock, I need the correct clock tree.
Currently that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide a
clock to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
Because the X1 (MCO2 output) is the same net as 50 MHz ETH_REF_CLK
input. MCO2 output is routed on a SoC pin and that is connected
with a wire to ETH_REF_CLK SoC pin (input).
Ok I see, but I don't think you have to link both clocks.
If I don't, then MCO2 will not have any consumer and would be turned
off by the kernel.
I agree, but IMO the MCO clock should be declared with
CLK_IGNORE_UNUSED flag in stm32mp1 clock driver.
Why? It can be safely turned off if it is only used to supply ETHRX. And
if the clock tree is correctly modeled, that is what happens.
You're right. I think we could only add an optional clock inside dwmac
stm32 glue to take this phy clock (here MCO2)
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From: Marek Vasut <marex@denx.de> Date: 2021-01-30 18:38:14
On 1/29/21 4:19 PM, Alexandre TORGUE wrote:
On 1/26/21 8:11 PM, Marek Vasut wrote:
quoted
On 1/26/21 5:47 PM, Alexandre TORGUE wrote:
quoted
On 1/26/21 4:42 PM, Marek Vasut wrote:
quoted
On 1/26/21 4:40 PM, Alexandre TORGUE wrote:
quoted
On 1/26/21 1:59 PM, Marek Vasut wrote:
quoted
On 1/26/21 11:54 AM, Alexandre TORGUE wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling
currently does not
permit selecting the clock input from SoC pad. To make
things worse, the
implementation of this is partly present and is split
between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock parent
is incorrect.
Sorry but I don't understand which configuration is
missing. I think we can handle all possible cases for RMII.
At the glue layer (dwmac-stm32.c) clocks gates and syscfg
are set regarding device tree binding (see the tab in
dwmac-stm32.c). You could have a look here for more
details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well
frequency if you want to select this path. Our current
"clock tree" is done to fit with our ST reference boards
(we have more peripherals than PLL outputs so we have to
make choices). So yes for customer/partners boards this
clock tree has to be modified to better fit with the need
(either using assigned-clock-parent or by modifying
bootloader clock tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but
I might also be confused.
See Figure 83. Peripheral clock distribution for Ethernet in
the MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to
drive the PHY clock, and uses eth_clk_fb to supply
ETH_RX_CLK. However, the 50 MHz is sourced directly from
PLL4P, which then has to run at 50 MHz and that in turn
reduces clock frequency for other blocks connected to PLL4P
(e.g. SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without
using the ref_clk coming from the PHY. And yes I can
understand that the drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration
issue. Either you don't use PLL4P for Ethernet (what you're
doing) or you don't use PLL4P for SDMMC. But yes, there are not
a lot of possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To
enable this entire chain of clock, I need the correct clock
tree. Currently that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide
a clock to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
Because the X1 (MCO2 output) is the same net as 50 MHz ETH_REF_CLK
input. MCO2 output is routed on a SoC pin and that is connected
with a wire to ETH_REF_CLK SoC pin (input).
Ok I see, but I don't think you have to link both clocks.
If I don't, then MCO2 will not have any consumer and would be turned
off by the kernel.
I agree, but IMO the MCO clock should be declared with
CLK_IGNORE_UNUSED flag in stm32mp1 clock driver.
Why? It can be safely turned off if it is only used to supply ETHRX.
And if the clock tree is correctly modeled, that is what happens.
You're right. I think we could only add an optional clock inside dwmac
stm32 glue to take this phy clock (here MCO2)
But you already do have clock in the glue, it's the ETHRX clock. There
are no additional clock that have to be added to the glue.
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On 1/26/21 11:54 AM, Alexandre TORGUE wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
quoted
quoted
The implementation of ETH_RX_CLK/ETH_REF_CLK handling
currently does not
permit selecting the clock input from SoC pad. To make
things worse, the
implementation of this is partly present and is split
between the clock
driver and dwmac4 driver. Moreover, the ETHRX clock
parent is incorrect.
Sorry but I don't understand which configuration is
missing. I think we can handle all possible cases for
RMII. At the glue layer (dwmac-stm32.c) clocks gates and
syscfg are set regarding device tree binding (see the tab
in dwmac-stm32.c). You could have a look here for more
details:
https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration
Regarding the clock parent, yes it is not at the well
frequency if you want to select this path. Our current
"clock tree" is done to fit with our ST reference boards
(we have more peripherals than PLL outputs so we have to
make choices). So yes for customer/partners boards this
clock tree has to be modified to better fit with the need
(either using assigned-clock-parent or by modifying
bootloader clock tree (tf-a or u-boot)).
I don't think you handle all the configuration options, but
I might also be confused.
See Figure 83. Peripheral clock distribution for Ethernet
in the MP1 datasheet for the below.
The current setup I have needs 50 MHz on SoC pad PA1 to
drive the PHY clock, and uses eth_clk_fb to supply
ETH_RX_CLK. However, the 50 MHz is sourced directly from
PLL4P, which then has to run at 50 MHz and that in turn
reduces clock frequency for other blocks connected to PLL4P
(e.g. SDMMC, where the impact is noticable).
Ok that's the common path to clock a PHY a 50MHz without
using the ref_clk coming from the PHY. And yes I can
understand that the drawback is huge).
So lets fix it.
There is no issue in code. It is just clock tree configuration
issue. Either you don't use PLL4P for Ethernet (what you're
doing) or you don't use PLL4P for SDMMC. But yes, there are
not a lot of possibilities.
I am supplying MCO2 with PLL4P, that is PLL4P->MCO2->ETHRX . To
enable this entire chain of clock, I need the correct clock
tree. Currently that cannot be modeled, can it?
Maybe I miss something, I thought your setup was like that:
First clock path to your PHY:
--------------------
PLL4P ---> MCO2 ---> X1 (PHY input clock which replaces crystal)
It is not directly linked to the dwmac-stm32. You "just" provide
a clock to MCO2. After that you can use MCO2 pins for any usages.
Second clock patch:
--------------------
50MHz (refclk coming from phy) --> ETH_REF_CLK pad
This one is already covered in dwmac-stm32.
Why do you want to link the both clock paths ?
Because the X1 (MCO2 output) is the same net as 50 MHz
ETH_REF_CLK input. MCO2 output is routed on a SoC pin and that is
connected with a wire to ETH_REF_CLK SoC pin (input).
Ok I see, but I don't think you have to link both clocks.
If I don't, then MCO2 will not have any consumer and would be
turned off by the kernel.
I agree, but IMO the MCO clock should be declared with
CLK_IGNORE_UNUSED flag in stm32mp1 clock driver.
Why? It can be safely turned off if it is only used to supply ETHRX.
And if the clock tree is correctly modeled, that is what happens.
You're right. I think we could only add an optional clock inside dwmac
stm32 glue to take this phy clock (here MCO2)
But you already do have clock in the glue, it's the ETHRX clock. There
are no additional clock that have to be added to the glue.
Yes this one is for ETHRX/REFCLK, but the one I talk about is the one to
clock the PHY (which replaces the crystal). In your case it is the same
net but it is not always the case.
cheers
alex
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