This series provides the Microchip Sparx5 Switch Reset Driver
The Sparx5 Switch SoC has a number of components that can be reset
individually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.
The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.
The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.
The Sparx5 Chip Register Model can be browsed at this location:
https://github.com/microchip-ung/sparx-5_reginfo
History:
v2 - v3: Removed unused headers
Renamed the reset controller dev member.
Use regmap_read_poll_timeout instead of polling a function.
Used two separate syscon entries in the binding
Simplified the syscon error handling.
Simplified the devm_reset_controller_register error handling.
Moved the contents of the mchp_sparx5_reset_config function into
the probe function.
v1 - v2: Removed debug prints
Changed the error handling to save the error code before jumping.
Steen Hegelund (3):
dt-bindings: reset: microchip sparx5 reset driver bindings
reset: mchp: sparx5: add switch reset driver
arm64: dts: reset: add microchip sparx5 switch reset driver
.../bindings/reset/microchip,rst.yaml | 59 +++++++++
arch/arm64/boot/dts/microchip/sparx5.dtsi | 14 +-
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 120 ++++++++++++++++++
5 files changed, 199 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
create mode 100644 drivers/reset/reset-microchip-sparx5.c
--
2.29.2
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@@ -0,0 +1,59 @@+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)+%YAML1.2+---+$id:"http://devicetree.org/schemas/reset/microchip,rst.yaml#"+$schema:"http://devicetree.org/meta-schemas/core.yaml#"++title:Microchip Sparx5 Switch Reset Controller++maintainers:+-Steen Hegelund <steen.hegelund@microchip.com>+-Lars Povlsen <lars.povlsen@microchip.com>++description:|+The Microchip Sparx5 Switch provides reset control and implements the following+functions+-One Time Switch Core Reset (Soft Reset)++properties:+$nodename:+pattern:"^reset-controller@[0-9a-f]+$"++compatible:+const:microchip,sparx5-switch-reset++reg:+maxItems:1++"#reset-cells":+const:1++cpu-syscon:+$ref:"/schemas/types.yaml#/definitions/phandle"+description:syscon used to access CPU reset+maxItems:1++gcb-syscon:+$ref:"/schemas/types.yaml#/definitions/phandle"+description:syscon used to access Global Control Block+maxItems:1++required:+-compatible+-reg+-"#reset-cells"+-cpu-syscon+-gcb-syscon++additionalProperties:false++examples:+-|+reset:reset-controller@0 {+compatible = "microchip,sparx5-switch-reset";+reg = <0x0 0x0>;+#reset-cells = <1>;+cpu-syscon = <&cpu_ctrl>;+gcb-syscon = <&gcb_ctrl>;+};+
--
2.29.2
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@@ -0,0 +1,59 @@+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)+%YAML1.2+---+$id:"http://devicetree.org/schemas/reset/microchip,rst.yaml#"+$schema:"http://devicetree.org/meta-schemas/core.yaml#"++title:Microchip Sparx5 Switch Reset Controller++maintainers:+-Steen Hegelund <steen.hegelund@microchip.com>+-Lars Povlsen <lars.povlsen@microchip.com>++description:|+The Microchip Sparx5 Switch provides reset control and implements the following+functions+-One Time Switch Core Reset (Soft Reset)++properties:+$nodename:+pattern:"^reset-controller@[0-9a-f]+$"++compatible:+const:microchip,sparx5-switch-reset++reg:+maxItems:1++"#reset-cells":+const:1++cpu-syscon:+$ref:"/schemas/types.yaml#/definitions/phandle"+description:syscon used to access CPU reset+maxItems:1++gcb-syscon:+$ref:"/schemas/types.yaml#/definitions/phandle"+description:syscon used to access Global Control Block+maxItems:1++required:+-compatible+-reg+-"#reset-cells"+-cpu-syscon+-gcb-syscon++additionalProperties:false++examples:+-|+reset:reset-controller@0 {+compatible = "microchip,sparx5-switch-reset";+reg = <0x0 0x0>;+#reset-cells = <1>;+cpu-syscon = <&cpu_ctrl>;+gcb-syscon = <&gcb_ctrl>;+};+
Hi,
This commit is also missing a commit message and you could probably get
some info from your cover letter here.
On 14/01/2021 17:24:31+0100, Steen Hegelund wrote:
Hi Alex,
On Tue, 2021-01-19 at 21:35 +0100, Alexandre Belloni wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you
know the content is safe
Hi,
Every patches need a commit message, even if in this case it will be
very small.
Yes that is a mistake. I will update the series.
On 14/01/2021 17:24:30+0100, Steen Hegelund wrote:
Hi Alex,
On Tue, 2021-01-19 at 21:37 +0100, Alexandre Belloni wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you
know the content is safe
Hi,
This commit is also missing a commit message and you could probably
get
some info from your cover letter here.
I will do that.
On 14/01/2021 17:24:31+0100, Steen Hegelund wrote:
help
This enables the reset controller driver for NXP
LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip
Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST