From: Kishon Vijay Abraham I <hidden> Date: 2021-01-04 12:44:08
AM64 uses the same PCIe controller as in J7200, however AM642 EVM
doesn't have a clock generator (unlike J7200 base board). Here
the clock from the SERDES has to be routed to the PCIE connector.
This series provides an option for the pci-j721e.c driver to
drive reference clock output to the connector.
v1 of the patch series can be found @ [1]
Changes from v1:
*) Fixed missing initialization of "ret" variable in the error path.
[1] -> http://lore.kernel.org/r/20201224115658.2795-1-kishon@ti.com
Kishon Vijay Abraham I (4):
dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the
connector
dt-bindings: pci: ti,j721e: Add host mode dt-bindings for TI's AM64
SoC
dt-bindings: pci: ti,j721e: Add endpoint mode dt-bindings for TI's
AM64 SoC
PCI: j721e: Add support to provide refclk to PCIe connector
.../bindings/pci/ti,j721e-pci-ep.yaml | 10 ++++---
.../bindings/pci/ti,j721e-pci-host.yaml | 27 ++++++++++++++-----
drivers/pci/controller/cadence/pci-j721e.c | 18 +++++++++++++
3 files changed, 45 insertions(+), 10 deletions(-)
--
2.17.1
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@@ -46,12 +46,21 @@ properties:maxItems:1clocks:-maxItems:1-description:clock-specifier to represent input to the PCIe+minItems:1+maxItems:2+description:clock-specifier to represent input to the PCIe for 1 item.+2nd item if present represents reference clock to the connector.clock-names:-items:--const:fck+oneOf:+-description:Represent input clock to the PCIe+items:+-const:fck+-description:Represent input clock to the PCIe and reference clock to+the connector.+items:+-const:fck+-const:pcie_refclkvendor-id:const:0x104c
--
2.17.1
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From: Kishon Vijay Abraham I <hidden> Date: 2021-01-04 12:42:44
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
@@ -16,12 +16,17 @@ allOf:properties:compatible:oneOf:--description:PCIe EP controller in J7200+-const:ti,am64-pcie-ep+-const:ti,j7200-pcie-ep+-const:ti,j721e-pcie-ep+-description:PCIe EP controller in AM64items:+-const:ti,am64-pcie-ep-const:ti,j7200-pcie-ep-const:ti,j721e-pcie-ep--description:PCIe EP controller in J721E+-description:PCIe EP controller in J7200items:+-const:ti,j7200-pcie-ep-const:ti,j721e-pcie-epreg:
From: Kishon Vijay Abraham I <hidden> Date: 2021-01-04 12:43:07
Add support to provide refclk to PCIe connector.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
drivers/pci/controller/cadence/pci-j721e.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
@@ -310,6 +312,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)structcdns_pcie_ep*ep;structgpio_desc*gpiod;void__iomem*base;+structclk*clk;u32num_lanes;u32mode;intret;
@@ -408,6 +411,20 @@ static int j721e_pcie_probe(struct platform_device *pdev)gotoerr_get_sync;}+clk=devm_clk_get_optional(dev,"pcie_refclk");+if(IS_ERR(clk)){+dev_err(dev,"failed to get pcie_refclk\n");+ret=PTR_ERR(clk);+gotoerr_pcie_setup;+}++ret=clk_prepare_enable(clk);+if(ret){+dev_err(dev,"failed to enable pcie_refclk\n");+gotoerr_get_sync;+}+pcie->refclk=clk;+/**"Power Sequencing and Reset Signal Timings"tablein*PCIEXPRESSCARDELECTROMECHANICALSPECIFICATION,REV.3.0
@@ -476,6 +493,7 @@ static int j721e_pcie_remove(struct platform_device *pdev)structcdns_pcie*cdns_pcie=pcie->cdns_pcie;structdevice*dev=&pdev->dev;+clk_disable_unprepare(pcie->refclk);cdns_pcie_disable_phy(cdns_pcie);pm_runtime_put(dev);pm_runtime_disable(dev);
--
2.17.1
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From: Kishon Vijay Abraham I <hidden> Date: 2021-01-04 12:44:08
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in
J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
@@ -16,12 +16,17 @@ allOf:properties:compatible:oneOf:--description:PCIe controller in J7200+-const:ti,am64-pcie-host+-const:ti,j7200-pcie-host+-const:ti,j721e-pcie-host+-description:PCIe controller in AM64items:+-const:ti,am64-pcie-host-const:ti,j7200-pcie-host-const:ti,j721e-pcie-host--description:PCIe controller in J721E+-description:PCIe controller in J7200items:+-const:ti,j7200-pcie-host-const:ti,j721e-pcie-hostreg:
@@ -46,12 +46,21 @@ properties:maxItems:1clocks:-maxItems:1-description:clock-specifier to represent input to the PCIe+minItems:1+maxItems:2+description:clock-specifier to represent input to the PCIe for 1 item.+2nd item if present represents reference clock to the connector.clock-names:-items:--const:fck+oneOf:+-description:Represent input clock to the PCIe+items:+-const:fck+-description:Represent input clock to the PCIe and reference clock to+the connector.+items:+-const:fck+-const:pcie_refclk
Can be just:
minItems: 1
items:
- const: fck
- const: pcie_refclk
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From: Rob Herring <robh@kernel.org> Date: 2021-01-11 22:38:46
On Mon, Jan 04, 2021 at 06:11:01PM +0530, Kishon Vijay Abraham I wrote:
quoted hunk
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in
J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I <redacted>
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)