[PATCH] arm64: dts: mt8183: Add gce setting in display node
From: Bibby Hsieh <hidden>
Date: 2019-09-03 01:39:23
Also in:
dri-devel, linux-mediatek, lkml
Subsystem:
arm/mediatek soc support, the rest · Maintainers:
Matthias Brugger, AngeloGioacchino Del Regno, Linus Torvalds
In order to use GCE function, we need add some informations into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events). Signed-off-by: Bibby Hsieh <redacted> Signed-off-by: Yongqiang Niu <redacted> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5616d158a4fa..b7d294c1c5b4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi@@ -485,6 +485,11 @@ compatible = "mediatek,mt8183-display"; reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, + <CMDQ_EVENT_MUTEX_STREAM_DONE1>; }; ovl0: ovl@14008000 {
@@ -494,6 +499,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; ovl_2l0: ovl@14009000 {
@@ -503,6 +509,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; ovl_2l1: ovl@1400a000 {
@@ -512,6 +519,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; rdma0: rdma@1400b000 {
@@ -522,6 +530,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA0>; mediatek,larb = <&larb0>; mediatek,rdma_fifo_size = <5>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; rdma1: rdma@1400c000 {
@@ -532,6 +541,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA1>; mediatek,larb = <&larb0>; mediatek,rdma_fifo_size = <2>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; color0: color@1400e000 {
@@ -541,6 +551,7 @@ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; ccorr0: ccorr@1400f000 {
@@ -549,6 +560,7 @@ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; aal0: aal@14010000 {
@@ -558,6 +570,7 @@ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; gamma0: gamma@14011000 {
@@ -567,6 +580,7 @@ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; dither0: dither@14012000 {
@@ -575,6 +589,7 @@ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; mutex: mutex@14016000 {
--
2.18.0
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