ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
From: John Garry <hidden> Date: 2018-10-15 11:18:10
On 15/10/2018 09:36, Zhen Lei wrote:
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
Can you add a better opening than the ITS translation register map?
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
I think arm_smmu_device.sync_count is better, or "sync_count member in
the the smmu driver control struct".
luckly that the previous and the next neighbour of "sync_count" are both aligned
/s/luckly/luckily or fortunately/
quoted hunk
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
Can you add a better opening than the ITS translation register map?
OK
quoted
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
I think arm_smmu_device.sync_count is better, or "sync_count member in the the smmu driver control struct".
OK, I will use "struct" in v2.
+ struct {
u32 sync_count;
+ u32 padding;
+ } __attribute__((aligned(8)));
quoted
luckly that the previous and the next neighbour of "sync_count" are both aligned
/s/luckly/luckily or fortunately/
OK, thanks
quoted
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
Can you indent these 2 members? However - as discussed internally - this may have endian issue so better to declare full 64b struct.
These indent is inherited, to keep aligning with other members.
There is no endian issue, I have tested it on both little-endian and big-endian.
$gdb vmlinux
......
(gdb) p &((struct arm_smmu_device *)0)->sync_count
$1 = (u32 *) 0x4178
(gdb) p &((struct arm_smmu_device *)0)->tst1
$2 = (int *) 0x4170
(gdb) p &((struct arm_smmu_device *)0)->tst2
$3 = (int *) 0x4180
------------testcase--------
From: Robin Murphy <robin.murphy@arm.com> Date: 2018-10-15 13:52:58
On 15/10/18 09:36, Zhen Lei wrote:
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
Surely the u64 member inherently makes the union, and thus the u32
member as well, 64-bit-aligned anyway?
Robin.
quoted hunk
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
Surely the u64 member inherently makes the union, and thus the u32 member as well, 64-bit-aligned anyway?
Yes, we really only need one step, "1." or "2.". As John Garry suggested, I will change it to "struct" mode.
Robin.
quoted
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
From: Will Deacon <hidden> Date: 2018-10-15 17:21:54
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
quoted hunk
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
Won't this already be aligned by the ABI?
Anyway, you'll need to swizzle things for big-endian, I suspect. Maybe you
can do something clever like making sync_count an array of two elements
and determining the offset based on the endianness. Or just keep it simple
like we do for things like struct qrwlock and struct qspinlock and use
#ifdefs.
Also -- you need a comment to explain this insanity :)
Will
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
quoted
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
Won't this already be aligned by the ABI?
Anyway, you'll need to swizzle things for big-endian, I suspect. Maybe you
can do something clever like making sync_count an array of two elements
and determining the offset based on the endianness. Or just keep it simple
like we do for things like struct qrwlock and struct qspinlock and use
#ifdefs.
This workaround is a special case, the sync_count is only written by ITS hardware,
and is only read by software. Although Hisilicon ITS will write 8 bytes at
MSIAddress(required it aligned by 8 bytes), but it can sure that the value of
MSIdata will be written at the lower 4 bytes(the start address of sync_count).
Because the type of sync_count is u32, so that CPU is also read the 4 bytes at
the lower address.
Also -- you need a comment to explain this insanity :)
Will
.
From: Robin Murphy <robin.murphy@arm.com> Date: 2018-10-16 09:48:40
On 15/10/18 18:21, Will Deacon wrote:
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
quoted
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
Won't this already be aligned by the ABI?
Anyway, you'll need to swizzle things for big-endian, I suspect. Maybe you
can do something clever like making sync_count an array of two elements
and determining the offset based on the endianness. Or just keep it simple
like we do for things like struct qrwlock and struct qspinlock and use
#ifdefs.
I don't think so - the CPUs should only ever be making word accesses to
the u32 member, while the SMMU expects to be writing little-endian data
to an ITS, so AFAICS the data word will always be at the lower address
either way.
Although now that it's come up, the pre-existing issue of whether the
byte order *within* that u32 comes out correct after its round-trip
through the SMMU is something I need to run away and hurriedly think
about...
Robin.
From: Will Deacon <hidden> Date: 2018-10-16 10:08:01
On Mon, Oct 15, 2018 at 06:36:52PM +0100, Robin Murphy wrote:
On 15/10/18 18:21, Will Deacon wrote:
quoted
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
quoted
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
Won't this already be aligned by the ABI?
Anyway, you'll need to swizzle things for big-endian, I suspect. Maybe you
can do something clever like making sync_count an array of two elements
and determining the offset based on the endianness. Or just keep it simple
like we do for things like struct qrwlock and struct qspinlock and use
#ifdefs.
I don't think so - the CPUs should only ever be making word accesses to the
u32 member, while the SMMU expects to be writing little-endian data to an
ITS, so AFAICS the data word will always be at the lower address either way.
Yes, thanks. I'd actually got the union layout wrong in my head and not
realised that both member will start at the same address. Ok, so that works.
Although now that it's come up, the pre-existing issue of whether the byte
order *within* that u32 comes out correct after its round-trip through the
SMMU is something I need to run away and hurriedly think about...
Ha, oops! Everything going into the command queue is swabbed, so I guess we
need to swab the data again in smp_cond_load_acquire(). I'll leave it with
you...
Will
From: Andrew Murray <hidden> Date: 2018-10-16 09:48:52
Hi Zhen,
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
My understanding is that MSI's are 32bit memory writes and as such the SMMU
performs a 32bit write in response to the MSI. If so then what is different
with the Hi16xx that causes a problem? Have you been able to able to adjust
the layout of the arm_smmu_device struct to demonstrate this?
Thanks,
Andrew Murray
quoted hunk
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
--
1.8.3
_______________________________________________
iommu mailing list
iommu at lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
Hi Zhen,
On Mon, Oct 15, 2018 at 04:36:16PM +0800, Zhen Lei wrote:
quoted
ITS translation register map:
0x0000-0x003C Reserved
0x0040 GITS_TRANSLATER
0x0044-0xFFFC Reserved
The standard GITS_TRANSLATER register in ITS is only 4 bytes, but Hisilicon
expands the next 4 bytes to carry some IMPDEF information. That means, 8 bytes
data will be written to MSIAddress each time.
MSIAddr: |----4bytes----|----4bytes----|
| MSIData | IMPDEF |
There is no problem for ITS, because the next 4 bytes space is reserved in ITS.
But it will overwrite the 4 bytes memory following "sync_count". It's very
luckly that the previous and the next neighbour of "sync_count" are both aligned
by 8 bytes, so no problem is met now.
My understanding is that MSI's are 32bit memory writes and as such the SMMU
performs a 32bit write in response to the MSI. If so then what is different
with the Hi16xx that causes a problem? Have you been able to able to adjust
the layout of the arm_smmu_device struct to demonstrate this?
In normal, only 32bits MSIdata will be written into sync_count:
|----4bytes----|----4bytes----|
| sync_count | xxxx |
But for Hi16xx, the ITS hardware will write extra 32bits IMDDEF data into "xxxx". If
"xxxx" is the space of the next struct member, its value will be overwritten.
Thanks,
Andrew Murray
quoted
It's good to explicitly add a workaround:
1. Add gcc __attribute__((aligned(8))) to make sure that "sync_count" is always
aligned by 8 bytes.
2. Add a "u64" union member to make sure the 4 bytes padding is always exist.
There is no functional change.
Signed-off-by: Zhen Lei <redacted>
---
drivers/iommu/arm-smmu-v3.c | 3 +++
1 file changed, 3 insertions(+)
--
1.8.3
_______________________________________________
iommu mailing list
iommu at lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu