@@ -0,0 +1,46 @@
+Actions Semi Owl SoCs SIRQ interrupt controller
+
+S500, S700 and S900 SoC's from Actions provides 3 SPI's from GIC,
+in which external interrupt controller can be connected. 3 SPI's
+45, 46, 47 from GIC are directly exposed as SIRQ. It has
+the following properties:
+
+- inputs three interrupt signal from external interrupt controller
+
+Required properties:
+
+- compatible: should be "actions,owl-sirq"
+- reg: physical base address of the controller and length of memory mapped.
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+  source, should be 2.
+- actions,sirq-shared-reg: Applicable for S500 and S700 where SIRQ register
+  details are maintained at same offset/register.
+- actions,sirq-offset: register offset for SIRQ interrupts. When registers are
+  shared, all the three offsets will be same (S500 and S700).
+- actions,sirq-clk-sel: external interrupt controller can be either
+  connected to 32Khz or 24Mhz external/internal clock. This needs
+  to be configured for per SIRQ line. Failing defaults to 32Khz clock.
+
+Example for S900:
+
+sirq: interrupt-controller at e01b0000 {
+	compatible = "actions,owl-sirq";
+	reg = <0 0xe01b0000 0 0x1000>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+	actions,sirq-clk-sel = <0 0 0>;
+	actions,sirq-offset = <0x200 0x528 0x52c>;
+};
+
+Example for S500 and S700:
+
+sirq: interrupt-controller at e01b0000 {
+	compatible = "actions,owl-sirq";
+	reg = <0 0xe01b0000 0 0x1000>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+	actions,sirq-shared-reg;
+	actions,sirq-clk-sel = <0 0 0>;
+	actions,sirq-offset = <0x200 0x200 0x200>;
+};