For Synopsys DesignWare 8250 uart which version >= 4.00a, there's a
valid divisor latch fraction register. The fractional divisor width is
4bits ~ 6bits.
patch1 introduces necessary hooks to 8250 core.
patch2 exports serial8250_do_set_divisor()
patch3 implements the fractional divisor support for Synopsys DW 8250.
Since v3:
- simplify the dw8250_get_divisor() implementation again.
Since v2:
- rebase to tty-next branch, since I need one patch from Andy which
is in tty-next
- drop the patch "serial: 8250: let serial8250_get_divisor() get
uart_port * as param" since it's in tty-next now.
- add a new patch to export serial8250_do_set_divisor(), and reuse it
to complete dw8250_set_divisor().
- remove DW 8250 version check, since the DLF register always exists
and if fractional divisor isn't supported, the register read as 0
- add comments to explain how dw8250_get_divisor() get quot and frac.
- the frac calcuation is simplified with well implemented GENMASK
- Add Andy's Reviewed-by tag to patch1.
Since v1:
- add an extra patch to let serial8250_get_divisor() get uart_port *
as param
- take Andy's suggestions to "integrates hooks in the same way like
it's done for the rest of 8250 ones". Many thanks to Andy.
Jisheng Zhang (3):
serial: 8250: introduce get_divisor() and set_divisor() hook
serial: 8250: export serial8250_do_set_divisor()
serial: 8250_dw: add fractional divisor support
drivers/tty/serial/8250/8250_core.c | 4 +++
drivers/tty/serial/8250/8250_dw.c | 45 +++++++++++++++++++++++++++++
drivers/tty/serial/8250/8250_port.c | 30 +++++++++++++++----
include/linux/serial_8250.h | 3 ++
include/linux/serial_core.h | 7 +++++
5 files changed, 84 insertions(+), 5 deletions(-)
--
2.18.0
Add these two hooks so that they can be overridden with driver specific
implementations.
Signed-off-by: Jisheng Zhang <redacted>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/tty/serial/8250/8250_core.c | 4 ++++
drivers/tty/serial/8250/8250_port.c | 27 +++++++++++++++++++++++----
include/linux/serial_core.h | 7 +++++++
3 files changed, 34 insertions(+), 4 deletions(-)
Some drivers could call serial8250_do_set_divisor() to complete its
own set_divisor routine. Export this symbol for code reusing.
Signed-off-by: Jisheng Zhang <redacted>
---
drivers/tty/serial/8250/8250_port.c | 5 +++--
include/linux/serial_8250.h | 3 +++
2 files changed, 6 insertions(+), 2 deletions(-)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: 2018-07-10 13:56:36
On Tue, 2018-07-10 at 11:13 +0800, Jisheng Zhang wrote:
Some drivers could call serial8250_do_set_divisor() to complete its
own set_divisor routine. Export this symbol for code reusing.
I dunno Greg's preferences here, but it could be merged with patch 1.
In any case,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
for this part.
For Synopsys DesignWare 8250 uart which version >= 4.00a, there's a
valid divisor latch fraction register. The fractional divisor width is
4bits ~ 6bits.
Now the preparation is done, it's easy to add the feature support.
This patch firstly tries to get the fractional divisor width during
probe, then setups dw specific get_divisor() and set_divisor() hook.
Signed-off-by: Jisheng Zhang <redacted>
---
drivers/tty/serial/8250/8250_dw.c | 45 +++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: 2018-07-10 16:19:30
On Tue, 2018-07-10 at 11:15 +0800, Jisheng Zhang wrote:
For Synopsys DesignWare 8250 uart which version >= 4.00a, there's a
valid divisor latch fraction register. The fractional divisor width is
4bits ~ 6bits.
Now the preparation is done, it's easy to add the feature support.
This patch firstly tries to get the fractional divisor width during
probe, then setups dw specific get_divisor() and set_divisor() hook.
Thanks for an update, my comments below.
+/*
+ * divisor = div(I) + div(F)
+ * "I" means integer, "F" means fractional
+ * quot = div(I) = clk / (16 * baud)
+ * frac = div(F) * 2^dlf_size
+ *
+ * let rem = clk % (16 * baud)
+ * we have: div(F) * (16 * baud) = rem
+ * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16
* baud)
+ */
+static unsigned int dw8250_get_divisor(struct uart_port *p,
+ unsigned int baud,
+ unsigned int *frac)
+{
While it looks indeed better, I would rather like to have a confirmation
it's working as designed.
For example, when I did some calculus, I cooked a preliminary check in
Python (easy and fast to prototype), for example:
https://gist.github.com/andy-shev/06b084488b3629898121 in Python, or
commit 9df461eca18f ("spi: pxa2xx: replace ugly table by approximation")
in the kernel.
Or another one here https://gist.github.com/andy-shev/8b2a73aeca2874f4cc
89 and commits c1a67b48f6a5 ("serial: 8250_pci: replace switch-case by
formula for Intel MID"), 21947ba654a6 ("serial: 8250_pci: replace
switch-case by formula")
P.S. The code itself looks good to me, thanks!
--
Andy Shevchenko [off-list ref]
Intel Finland Oy
Hi Andy,
On Tue, 10 Jul 2018 19:19:21 +0300 Andy Shevchenko wrote:
On Tue, 2018-07-10 at 11:15 +0800, Jisheng Zhang wrote:
quoted
For Synopsys DesignWare 8250 uart which version >= 4.00a, there's a
valid divisor latch fraction register. The fractional divisor width is
4bits ~ 6bits.
Now the preparation is done, it's easy to add the feature support.
This patch firstly tries to get the fractional divisor width during
probe, then setups dw specific get_divisor() and set_divisor() hook.
Thanks for an update, my comments below.
quoted
+/*
+ * divisor = div(I) + div(F)
+ * "I" means integer, "F" means fractional
+ * quot = div(I) = clk / (16 * baud)
+ * frac = div(F) * 2^dlf_size
+ *
+ * let rem = clk % (16 * baud)
+ * we have: div(F) * (16 * baud) = rem
+ * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16
* baud)
+ */
+static unsigned int dw8250_get_divisor(struct uart_port *p,
+ unsigned int baud,
+ unsigned int *frac)
+{
While it looks indeed better, I would rather like to have a confirmation
it's working as designed.
For example, when I did some calculus, I cooked a preliminary check in
Python (easy and fast to prototype), for example:
https://gist.github.com/andy-shev/06b084488b3629898121 in Python, or
commit 9df461eca18f ("spi: pxa2xx: replace ugly table by approximation")
in the kernel.
Or another one here https://gist.github.com/andy-shev/8b2a73aeca2874f4cc
89 and commits c1a67b48f6a5 ("serial: 8250_pci: replace switch-case by
formula for Intel MID"), 21947ba654a6 ("serial: 8250_pci: replace
switch-case by formula")
My python coding skill is limited. So I wrote a simple c program to
do the check for common clks and baudrate combination. All passed. I
paste the code here:
#include <stdio.h>
#include <assert.h>
#include <math.h>
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#define DIV_ROUND_CLOSEST(x, divisor)( \
{ \
typeof(x) __x = x; \
typeof(divisor) __d = divisor; \
(((typeof(x))-1) > 0 || \
((typeof(divisor))-1) > 0 || \
(((__x) > 0) == ((__d) > 0))) ? \
(((__x) + ((__d) / 2)) / (__d)) : \
(((__x) - ((__d) / 2)) / (__d)); \
} \
)
static unsigned int baud[] = {9600, 19200, 38400, 57600, 115200, 230400,
460800, 921600, 1843200, 3250000, 4454400,
576000, 1152000, 500000, 1000000, 1500000,
2000000, 2500000, 3000000, 3500000, 4000000};
static unsigned int clk[] = {25000000, 50000000, 100000000, 133000000, 200000000};
static void check(int baud, int clk, int dlf_size)
{
unsigned int rem, frac, quot;
unsigned int base_baud = baud * 16;
float div, divf;
quot = clk / base_baud;
rem = clk % base_baud;
frac = DIV_ROUND_CLOSEST(rem << dlf_size, base_baud);
div = (float)clk / base_baud;
divf = div - (int)div;
divf *= (1 << dlf_size);
assert(quot == (int)div);
assert(frac == (int)round(divf));
printf("checked %d %d %d %d %d\n", baud, clk, dlf_size, quot, frac);
}
int main()
{
int i, j, k;
for (i = 0; i < ARRAY_SIZE(baud); i++) {
for (j = 0; j < ARRAY_SIZE(clk); j++) {
for (k = 4; k <= 6; k++) {
check(baud[i], clk[j], k);
}
}
}
return 0;
}
My python coding skill is limited. So I wrote a simple c program to
do the check for common clks and baudrate combination. All passed. I
paste the code here:
For Synopsys DesignWare 8250 uart which version >= 4.00a, there's a
valid divisor latch fraction register. The fractional divisor width is
4bits ~ 6bits.
Now the preparation is done, it's easy to add the feature support.
This patch firstly tries to get the fractional divisor width during
probe, then setups dw specific get_divisor() and set_divisor() hook.
Signed-off-by: Jisheng Zhang <redacted>
---
drivers/tty/serial/8250/8250_dw.c | 45 +++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Date: 2018-07-11 11:31:16
On Wed, 2018-07-11 at 15:11 +0800, Jisheng Zhang wrote:
For Synopsys DesignWare 8250 uart which version >= 4.00a, there's a
valid divisor latch fraction register. The fractional divisor width is
4bits ~ 6bits.
Now the preparation is done, it's easy to add the feature support.
This patch firstly tries to get the fractional divisor width during
probe, then setups dw specific get_divisor() and set_divisor() hook.
You would need to resend entire series as v6.
Don't forget to add given tags.
But, wait a bit, I would like to check the algo (thanks for C program!).
--
Andy Shevchenko [off-list ref]
Intel Finland Oy