[PATCH] CNS3xxx: Cosmetic: Fix misc register usage
From: khalasa@piap.pl (Krzysztof Hałasa)
Date: 2018-05-10 10:37:17
Subsystem:
arm port, the rest · Maintainers:
Russell King, Linus Torvalds
Signed-off-by: Krzysztof Ha?asa <khalasa@piap.pl>
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c@@ -395,7 +395,7 @@ static void __init cns3xxx_init(void) dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); if (of_device_is_available(dn)) { - u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); + u32 __iomem *gpioa = IOMEM(MISC_GPIOA_PIN_ENABLE_REG); u32 gpioa_pins = __raw_readl(gpioa); /* MMC/SD pins share with GPIOA */
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 7da78a2451f1..daafbe764a96 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c@@ -97,7 +97,7 @@ static struct platform_device cns3xxx_sdhci_pdev = { void __init cns3xxx_sdhci_init(void) { - u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); + u32 __iomem *gpioa = IOMEM(MISC_GPIOA_PIN_ENABLE_REG); u32 gpioa_pins = __raw_readl(gpioa); /* MMC/SD pins share with GPIOA */
--
Krzysztof Halasa
Industrial Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland