Hi Simon, Magnus,
This patch series adds the second Cortex-A57 CPU core, and the
Cortex-A53 L2 cache-controller and CPU nodes on the Renesas R-Car M3-W
SoC to its DTS file.
Note that these patches add hardware description; actual enabling of the
CPU depends on the PSCI firmware.
With the current firmware version (v2.16.0), only the CA57 CPU cores are
enabled, hence the last patch does not introduce undeterministic
scheduling behavior due to migration between big and LITTLE cores.
Tested on r8a7796/salvator-x, with CPU hot(un)plug and system suspend.
Thanks for applying!
Geert Uytterhoeven (2):
arm64: dts: r8a7796: Add CA53 L2 cache-controller node
arm64: dts: r8a7796: Add Cortex-A53 CPU cores
Takeshi Kihara (1):
arm64: dts: r8a7796: Add Cortex-A57 CPU cores
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 64 +++++++++++++++++++++++++++++---
1 file changed, 58 insertions(+), 6 deletions(-)
--
1.9.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
This patch adds Cortex-A53 CPU cores of R8A7796 SoC, and sets a total of
6 cores (2 x Cortex-A57 + 4 x Cortex-A53).
Based on a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 46 ++++++++++++++++++++++++++++----
1 file changed, 41 insertions(+), 5 deletions(-)
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
Hi Sudeep,
On Fri, Feb 17, 2017 at 6:51 PM, Sudeep Holla [off-list ref] wrote:
On 17/02/17 15:30, Geert Uytterhoeven wrote:
quoted
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
Is this not integrated L2 cache ? IIUC reg is MPIDR of the cpu and
representing it as cache controller with some reg value doesn't sound
correct IMO.
So this should be cache-controller-1, without a reg property?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Feb 17, 2017 at 8:07 PM, Geert Uytterhoeven
[off-list ref] wrote:
On Fri, Feb 17, 2017 at 6:51 PM, Sudeep Holla [off-list ref] wrote:
quoted
On 17/02/17 15:30, Geert Uytterhoeven wrote:
quoted
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
Is this not integrated L2 cache ? IIUC reg is MPIDR of the cpu and
representing it as cache controller with some reg value doesn't sound
correct IMO.
So this should be cache-controller-1, without a reg property?
BTW, that means the advice from https://lkml.org/lkml/2016/3/8/80:
| Just add a reg property. The values should probably match the MPIDR in
| some way (e.g. 0 and 100).
was wrong, and we should fix all cache-controller nodes that got "fixed"?
Having better DT documentation for caches on ARM would be nice...
There's only a (too) minimalist example in
Documentation/devicetree/bindings/arm/cpu-capacity.txt
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Fri, Feb 17, 2017 at 8:07 PM, Geert Uytterhoeven
[off-list ref] wrote:
quoted
On Fri, Feb 17, 2017 at 6:51 PM, Sudeep Holla [off-list ref] wrote:
quoted
On 17/02/17 15:30, Geert Uytterhoeven wrote:
quoted
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
Is this not integrated L2 cache ? IIUC reg is MPIDR of the cpu and
representing it as cache controller with some reg value doesn't sound
correct IMO.
So this should be cache-controller-1, without a reg property?
BTW, that means the advice from https://lkml.org/lkml/2016/3/8/80:
| Just add a reg property. The values should probably match the MPIDR in
| some way (e.g. 0 and 100).
was wrong, and we should fix all cache-controller nodes that got "fixed"?
OK. IMO it's cpu peripheral which has no mmio similar to architected
timers that are accessed via system registers. So representing them with
reg = mpidr sounds not correct. If DT maintainers are OK with such
representation, it should be fine but better to document it.
Having better DT documentation for caches on ARM would be nice...
There's only a (too) minimalist example in
Documentation/devicetree/bindings/arm/cpu-capacity.txt
On Fri, Feb 17, 2017 at 04:30:32PM +0100, Geert Uytterhoeven wrote:
Hi Simon, Magnus,
This patch series adds the second Cortex-A57 CPU core, and the
Cortex-A53 L2 cache-controller and CPU nodes on the Renesas R-Car M3-W
SoC to its DTS file.
Note that these patches add hardware description; actual enabling of the
CPU depends on the PSCI firmware.
With the current firmware version (v2.16.0), only the CA57 CPU cores are
enabled, hence the last patch does not introduce undeterministic
scheduling behavior due to migration between big and LITTLE cores.
Tested on r8a7796/salvator-x, with CPU hot(un)plug and system suspend.
Thanks for applying!
Geert Uytterhoeven (2):
arm64: dts: r8a7796: Add CA53 L2 cache-controller node
arm64: dts: r8a7796: Add Cortex-A53 CPU cores
Takeshi Kihara (1):
arm64: dts: r8a7796: Add Cortex-A57 CPU cores
Hi Geert,
thanks for your work in this area.
There seems to be some more work required to get patch 2/3 across the line
so I am holding off on applying this series for now.