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From: Ramana Radhakrishnan <hidden>
Date: 2016-12-01 10:00:59
By the way, how is this implemented? Some of them overlap existing callee-saved registers.
The AArch64 PCS requires that only the bottom 64 bits of SIMD registers (v8-v15) are callee-saved. The top 64 bits of the current Advanced SIMD registers are the responsibility of the caller. This naturally extends to SVE. Ramana