[PATCH 2/3] Documentation: DT: add LS1012A compatible for SCFG and DCFG
From: Harninder Rai <hidden>
Date: 2016-11-09 18:04:39
Also in:
linux-devicetree
Subsystem:
open firmware and flattened device tree bindings, the rest · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Signed-off-by: Harninder Rai <redacted> Signed-off-by: Bhaskar Upadhaya <redacted> --- Documentation/devicetree/bindings/arm/fsl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 3b01338..c9c567a 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt@@ -108,7 +108,7 @@ status. - compatible: Should contain a chip-specific compatible string, Chip-specific strings are of the form "fsl,<chip>-scfg", The following <chip>s are known to be supported: - ls1021a, ls1043a, ls1046a, ls2080a. + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - reg: should contain base address and length of SCFG memory-mapped registers
@@ -126,7 +126,7 @@ core start address and release the secondary core from holdoff and startup. - compatible: Should contain a chip-specific compatible string, Chip-specific strings are of the form "fsl,<chip>-dcfg", The following <chip>s are known to be supported: - ls1021a, ls1043a, ls1046a, ls2080a. + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. - reg : should contain base address and length of DCFG memory-mapped registers
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2.7.4