[PATCH 01/10] dt-bindings: Add compatible property for LS1012A

@@ -119,7 +119,7 @@ Freescale DCFG
 configuration and status for the device. Such as setting the secondary
 core start address and release the secondary core from holdoff and startup.
   Required properties:
-  - compatible: should be "fsl,ls1021a-dcfg"
+  - compatible: can be "fsl,ls1021a-dcfg", "fsl,ls1012a-dcfg", "fsl,ls1043a-dcfg"
   - reg : should contain base address and length of DCFG memory-mapped registers
 
 Example:

@@ -151,3 +151,14 @@ LS2080A ARMv8 based RDB Board
 Required root node properties:
     - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
 
+LS1012A ARMv8 based FRDM Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
+LS1012A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
+
+LS1012A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,ls1012a-qds", "fsl,ls1012a";

@@ -7,9 +7,9 @@ This file documents differences between the core properties described
 by mmc.txt and the properties used by the sdhci-esdhc driver.
 
 Required properties:
+  - compatible : "fsl,mpc8378-esdhc", "fsl,ls1012a-esdhc0", "fsl,ls1012a-esdhc1".
   - interrupt-parent : interrupt source phandle.
   - clock-frequency : specifies eSDHC base clock frequency.
-
 Optional properties:
   - sdhci,wp-inverted : specifies that eSDHC controller reports
     inverted write-protect state; New devices should use the generic

@@ -3,7 +3,7 @@
 Required properties:
   - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
 		 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",
-		 "fsl,ls1021a-qspi"
+		 "fsl,ls1012a-qspi, "fsl,ls1021a-qspi"
 		 or
 		 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
 		 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"

@@ -13,6 +13,7 @@ Required properties:
                  at25df321a
                  at25df641
                  at26df081a
+		 eon,en25s64
                  mr25h256
                  mx25l4005a
                  mx25l1606e

@@ -29,6 +30,7 @@ Required properties:
                  s25fl008k
                  s25fl064k
                  sst25vf040b
+		 sst,sst25wf040b
                  m25p40
                  m25p80
                  m25p16

@@ -15,6 +15,7 @@ Required properties:
 - compatible: should contain the platform identifier such as:
         "fsl,ls1021a-pcie", "snps,dw-pcie"
         "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
+	"fsl,ls1012a-pcie", "fsl,ls1043a-pcie" ,"snps,dw-pcie"
 - reg: base addresses and lengths of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.

@@ -2,6 +2,7 @@ ARM Freescale DSPI controller
 
 Required properties:
 - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
+		"fsl,ls1012a-dspi", "fsl,ls1043a-dspi",
 		"fsl,ls2085a-dspi"
 		or
 		"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"

@@ -1,7 +1,7 @@
 * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
 
 Required properties:
-- compatible : Must include "fsl,qoriq-tmu". The version of the device is
+- compatible :"fsl,qoriq-tmu", "fsl,ls1012a-tmu". The version of the device is
 	determined by the TMU IP Block Revision Register (IPBRR0) at
 	offset 0x0BF8.
 	Table of correspondences between IPBRR0 values and example  chips:

@@ -81,3 +81,13 @@ Example dual role USB controller device node for MPC5121ADS:
 		fsl,invert-drvvbus;
 		fsl,invert-pwr-fault;
 	};
+
+Example dual role USB controller device node for LS1012A:
+	usb at 8600000 {
+		compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+		reg = <0x0 0x8600000 0x0 0x1000>;
+		interrupts = <0 139 0x4>;
+		dr_mode = "host";
+		phy_type = "ulpi";
+		fsl,usb-erratum-a005697;
+	};

@@ -85,6 +85,7 @@ elan	Elan Microelectronic Corp.
 embest	Shenzhen Embest Technology Co., Ltd.
 emmicro	EM Microelectronic
 energymicro	Silicon Laboratories (formerly Energy Micro AS)
+eon	Eon Silicon Solution, Inc.
 epcos	EPCOS AG
 epfl	Ecole Polytechnique F?d?rale de Lausanne
 epson	Seiko Epson Corp.

@@ -246,6 +247,7 @@ solomon        Solomon Systech Limited
 sony	Sony Corporation
 spansion	Spansion Inc.
 sprd	Spreadtrum Communications Inc.
+sst	Silicon Storage Technology, Inc.
 st	STMicroelectronics
 startek	Startek
 ste	ST-Ericsson

@@ -0,0 +1,153 @@
+SEC 5 is Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
+Currently Freescale arm chip LS1012A is embedded with SEC 5.
+SEC 5 device tree binding include:
+   -SEC 5 Node
+   -Job Ring Node
+   -Full Example
+
+=====================================================================
+SEC 5 Node
+
+Description
+
+    Node defines the base address of the SEC 5 block.
+    This block specifies the address range of all global
+    configuration registers for the SEC 5 block.
+    For example, In LS1012A, we could see three SEC 5 node.
+
+PROPERTIES
+
+   - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v5.4".
+
+   - fsl,sec-era
+      Usage: optional
+      Value type: <u32>
+      Definition: A standard property. Define the 'ERA' of the SEC
+          device.
+
+   - #address-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing physical addresses in child nodes.
+
+   - #size-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing the size of physical addresses in
+           child nodes.
+
+   - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the physical
+          address and length of the SEC 5 configuration registers.
+
+   - ranges
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: A standard property.  Specifies the physical address
+           range of the SEC 5.0 register space (-SNVS not included).  A
+           triplet that includes the child address, parent address, &
+           length.
+
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+
+EXAMPLE
+	crypto: crypto at 1700000 {
+                        compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+                                     "fsl,sec-v4.0";
+                        fsl,sec-era = <8>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x0 0x00 0x1700000 0x100000>;
+                        reg = <0x00 0x1700000 0x0 0x100000>;
+                        interrupts = <0 75 0x4>;
+	}
+
+=====================================================================
+Job Ring (JR) Node
+
+    Child of the crypto node defines data processing interface to SEC 5
+    across the peripheral bus for purposes of processing
+    cryptographic descriptors. The specified address
+    range can be made visible to one (or more) cores.
+    The interrupt defined for this node is controlled within
+    the address range of this node.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v5.4-job-ring".
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: Specifies a two JR parameters:  an offset from
+           the parent physical address and the length the JR registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop_encoded-array>
+      Definition:  Specifies the interrupts generated by this
+           device.  The value of the interrupts property
+           consists of one interrupt specifier. The format
+           of the specifier is defined by the binding document
+           describing the node's interrupt parent.
+
+EXAMPLE
+	sec_jr0: jr at 10000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x10000 0x10000>;
+			interrupts = <0 71 0x4>;
+	};
+
+===================================================================
+Full Example
+
+Since some chips may contain more than one SEC, the dtsi contains
+only the node contents, not the node itself.  A chip using the SEC
+should include the dtsi inside each SEC node.  Example:
+
+In fsl-ls1012a.dtsi:
+
+	compatible = "fsl,sec-v5.4";
+	fsl,sec-era = <8>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	sec_jr0: jr at 10000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x10000 0x10000>;
+			interrupts = <0 71 0x4>;
+	};
+	sec_jr1: jr at 20000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x20000 0x10000>;
+			interrupts = <0 72 0x4>;
+	};
+	sec_jr2: jr at 30000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x30000 0x10000>;
+			interrupts = <0 73 0x4>;
+	};
+	sec_jr3: jr at 40000 {
+		compatible = "fsl,sec-v5.4-job-ring",
+			"fsl,sec-v5.0-job-ring",
+			"fsl,sec-v4.0-job-ring";
+			reg = <0x40000 0x10000>;
+			interrupts = <0 74 0x4>;
+	};