[PATCH 1/2] ARM: dts: imx27-phytec-phycore-som: Add simple-card support for PMIC

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2 messages, 1 author, 2016-06-18 · open the first message on its own page

[PATCH 1/2] ARM: dts: imx27-phytec-phycore-som: Add simple-card support for PMIC

From: Alexander Shiyan <hidden>
Date: 2016-06-18 17:09:11 

This patch adds simple-card support for the MC13783 PMIC.

Signed-off-by: Alexander Shiyan <redacted>
---
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index b4e955e..9908b42 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -80,6 +80,7 @@
 	status = "okay";
 
 	pmic: mc13783 at 0 {
+		#sound-dai-cells = <0>;
 		compatible = "fsl,mc13783";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pmic>;
-- 
2.4.9

[PATCH 2/2] ARM: dts: imx27-phytec-phycore-som: Move AUDMUX pins under AUDMUX node

From: Alexander Shiyan <hidden>
Date: 2016-06-18 17:09:12 

AUDMUX node should be used for the AUDMUX corresponding pins.

Signed-off-by: Alexander Shiyan <redacted>
---
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index 9908b42..f19d1f5b 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -58,6 +58,8 @@
 };
 
 &audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
 	status = "okay";
 
 	/* SSI0 <=> PINS_4 (MC13783 Audio) */
@@ -213,6 +215,15 @@
 
 &iomuxc {
 	imx27_phycore_som {
+		pinctrl_audmux: audmuxgrp {
+			fsl,pins = <
+				MX27_PAD_SSI1_FS__SSI1_FS		0x0
+				MX27_PAD_SSI1_RXDAT__SSI1_RXDAT		0x0
+				MX27_PAD_SSI1_TXDAT__SSI1_TXDAT		0x0
+				MX27_PAD_SSI1_CLK__SSI1_CLK		0x0
+			>;
+		};
+
 		pinctrl_cspi1: cspi1grp {
 			fsl,pins = <
 				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
@@ -271,15 +282,6 @@
 			>;
 		};
 
-		pinctrl_ssi1: ssi1grp {
-			fsl,pins = <
-				MX27_PAD_SSI1_FS__SSI1_FS 0x0
-				MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
-				MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
-				MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
-			>;
-		};
-
 		pinctrl_usbotg: usbotggrp {
 			fsl,pins = <
 				MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
@@ -309,8 +311,6 @@
 };
 
 &ssi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ssi1>;
 	status = "okay";
 };
 
-- 
2.4.9
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