[PATCH 1/2] arm64: dts: ls1043a: Add cache nodes for cacheinfo support

Subsystems: arm/freescale imx / mxc / layerscape arm architecture, the rest

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3 messages, 2 authors, 2016-06-21 · open the first message on its own page

[PATCH 1/2] arm64: dts: ls1043a: Add cache nodes for cacheinfo support

From: Li Yang <hidden>
Date: 2016-06-17 00:09:57 

Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <redacted>
---
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index de0323b..2b4aa2a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -65,6 +65,7 @@
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x0>;
 			clocks = <&clockgen 1 0>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu1: cpu at 1 {
@@ -72,6 +73,7 @@
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x1>;
 			clocks = <&clockgen 1 0>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu2: cpu at 2 {
@@ -79,6 +81,7 @@
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x2>;
 			clocks = <&clockgen 1 0>;
+			next-level-cache = <&l2>;
 		};
 
 		cpu3: cpu at 3 {
@@ -86,6 +89,11 @@
 			compatible = "arm,cortex-a53";
 			reg = <0x0 0x3>;
 			clocks = <&clockgen 1 0>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache {
+			compatible = "cache";
 		};
 	};
 
-- 
1.9.0

[PATCH 2/2] arm64: dts: ls2080a: Add cache nodes for cacheinfo support

From: Li Yang <hidden>
Date: 2016-06-17 00:10:46 

Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <redacted>
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 3187c82..0f4b9c1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -67,6 +67,7 @@
 			compatible = "arm,cortex-a57";
 			reg = <0x0 0x0>;
 			clocks = <&clockgen 1 0>;
+			next-level-cache = <&cluster0_l2>;
 		};
 
 		cpu at 1 {
@@ -74,6 +75,7 @@
 			compatible = "arm,cortex-a57";
 			reg = <0x0 0x1>;
 			clocks = <&clockgen 1 0>;
+			next-level-cache = <&cluster0_l2>;
 		};
 
 		cpu at 100 {
@@ -81,6 +83,7 @@
 			compatible = "arm,cortex-a57";
 			reg = <0x0 0x100>;
 			clocks = <&clockgen 1 1>;
+			next-level-cache = <&cluster1_l2>;
 		};
 
 		cpu at 101 {
@@ -88,6 +91,7 @@
 			compatible = "arm,cortex-a57";
 			reg = <0x0 0x101>;
 			clocks = <&clockgen 1 1>;
+			next-level-cache = <&cluster1_l2>;
 		};
 
 		cpu at 200 {
@@ -95,6 +99,7 @@
 			compatible = "arm,cortex-a57";
 			reg = <0x0 0x200>;
 			clocks = <&clockgen 1 2>;
+			next-level-cache = <&cluster2_l2>;
 		};
 
 		cpu at 201 {
@@ -102,6 +107,7 @@
 			compatible = "arm,cortex-a57";
 			reg = <0x0 0x201>;
 			clocks = <&clockgen 1 2>;
+			next-level-cache = <&cluster2_l2>;
 		};
 
 		cpu at 300 {
@@ -109,6 +115,7 @@
 			compatible = "arm,cortex-a57";
 			reg = <0x0 0x300>;
 			clocks = <&clockgen 1 3>;
+			next-level-cache = <&cluster3_l2>;
 		};
 
 		cpu at 301 {
@@ -116,6 +123,23 @@
 			compatible = "arm,cortex-a57";
 			reg = <0x0 0x301>;
 			clocks = <&clockgen 1 3>;
+			next-level-cache = <&cluster3_l2>;
+		};
+
+		cluster0_l2: l2-cache0 {
+			compatible = "cache";
+		};
+
+		cluster1_l2: l2-cache1 {
+			compatible = "cache";
+		};
+
+		cluster2_l2: l2-cache2 {
+			compatible = "cache";
+		};
+
+		cluster3_l2: l2-cache3 {
+			compatible = "cache";
 		};
 	};
 
-- 
1.9.0

Re: [PATCH 1/2] arm64: dts: ls1043a: Add cache nodes for cacheinfo support

From: Shawn Guo <shawnguo@kernel.org>
Date: 2016-06-21 06:46:10 

On Thu, Jun 16, 2016 at 06:35:03PM -0500, Li Yang wrote:
Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: Li Yang <redacted>
Applied both, thanks.
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