[PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled

All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped.

For the i.MX6 specific L2 cache handling we missed this check.
Add it.

Signed-off-by: Marcel Grosshans <redacted>
Signed-off-by: Dirk Behme <redacted>
---
 arch/arm/mach-imx/system.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 51c3501..a600bd7 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c

@@ -106,6 +106,9 @@ void __init imx_init_l2cache(void)
 		goto out;
 	}
 
+	if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)
+		goto skip_if_enabled;
+
 	/* Configure the L2 PREFETCH and POWER registers */
 	val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
 	val |= 0x70800000;

@@ -122,6 +125,7 @@ void __init imx_init_l2cache(void)
 		val &= ~(1 << 30 | 1 << 23);
 	writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
 
+skip_if_enabled:
 	iounmap(l2x0_base);
 	of_node_put(np);
 

-- 
2.5.0

On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:

All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped.

For the i.MX6 specific L2 cache handling we missed this check.
Add it.

What's the reasoning behind this?  The prefetch register is writable
while the L2 cache is enabled, unlike the auxiliary control register.

-- 
RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

On 12.02.2016 15:16, Russell King - ARM Linux wrote:

On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:

quoted

All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped.

For the i.MX6 specific L2 cache handling we missed this check.
Add it.

What's the reasoning behind this?  The prefetch register is writable
while the L2 cache is enabled, unlike the auxiliary control register.

 From an internal log I have the following info:

The write to the L2-Cache controller from non-secure world causes an 
imprecise
external abort. If Linux runs from normal world the cache controller 
is already
enabled and thus no configuration is needed by Linux.

Best regards

Dirk

On Fri, Feb 12, 2016 at 04:51:00PM +0100, Dirk Behme wrote:

On 12.02.2016 15:16, Russell King - ARM Linux wrote:

quoted

On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:

quoted

All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped.

For the i.MX6 specific L2 cache handling we missed this check.
Add it.

What's the reasoning behind this?  The prefetch register is writable
while the L2 cache is enabled, unlike the auxiliary control register.

From an internal log I have the following info:

The write to the L2-Cache controller from non-secure world causes an
imprecise
external abort. If Linux runs from normal world the cache controller
is already
enabled and thus no configuration is needed by Linux.

Dirk,

Do you have a real use case of this, i.e. running Linux on i.MX6 in
non-secure world?

Shawn

On 14.02.2016 09:18, Shawn Guo wrote:

On Fri, Feb 12, 2016 at 04:51:00PM +0100, Dirk Behme wrote:

quoted

On 12.02.2016 15:16, Russell King - ARM Linux wrote:

quoted

On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:

quoted

All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped.

For the i.MX6 specific L2 cache handling we missed this check.
Add it.

What's the reasoning behind this?  The prefetch register is writable
while the L2 cache is enabled, unlike the auxiliary control register.

 From an internal log I have the following info:

The write to the L2-Cache controller from non-secure world causes an
imprecise
external abort. If Linux runs from normal world the cache controller
is already
enabled and thus no configuration is needed by Linux.

Dirk,

Do you have a real use case of this, i.e. running Linux on i.MX6 in
non-secure world?

Yes, in a scenario where one of the cores runs a RTOS.


Best regards

Dirk

On Sun, Feb 14, 2016 at 09:30:06AM +0100, Dirk Behme wrote:

On 14.02.2016 09:18, Shawn Guo wrote:

quoted

On Fri, Feb 12, 2016 at 04:51:00PM +0100, Dirk Behme wrote:

quoted

On 12.02.2016 15:16, Russell King - ARM Linux wrote:

quoted

On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:

quoted

All the generic L2 cache handling code is encapsulated by a
check if the L2 cache is enabled. If it's enabled already, the code
is skipped.

For the i.MX6 specific L2 cache handling we missed this check.
Add it.

What's the reasoning behind this?  The prefetch register is writable
while the L2 cache is enabled, unlike the auxiliary control register.

From an internal log I have the following info:

The write to the L2-Cache controller from non-secure world causes an
imprecise
external abort. If Linux runs from normal world the cache controller
is already
enabled and thus no configuration is needed by Linux.

Dirk,

Do you have a real use case of this, i.e. running Linux on i.MX6 in
non-secure world?

Yes, in a scenario where one of the cores runs a RTOS.

Can you please reword the commit log to have the above non-secure world
user story mentioned in there?

Shawn