[PATCH v1 0/3] clk: rockchip: rk3368: fix some error for rk3368 clk

From: zhangqing <redacted>

modify edp_24m parent select bit.
enable CLK_SET_RATE_PARENT flag for spdif_8ch and i2s_2ch.

zhangqing (3):
  clk: rockchip: rk3368: fix edp_24m parent
  clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for
    spdif_8ch
  clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2ch

 drivers/clk/rockchip/clk-rk3368.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

-- 
1.9.1

From: zhangqing <redacted>

The edp_24m parent select bit define is:
1'b0:xin24m
1'b1:1'b0(dummy)
so adapt the parent sel bit to the currect one.

Signed-off-by: zhangqing <redacted>
---
 drivers/clk/rockchip/clk-rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index be0ede5..4885e6b 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c

@@ -121,7 +121,7 @@ PNAME(mux_i2s_2ch_p)		= { "i2s_2ch_src", "i2s_2ch_frac",
 				    "dummy", "xin12m" };
 PNAME(mux_spdif_8ch_p)		= { "spdif_8ch_pre", "spdif_8ch_frac",
 				    "ext_i2s", "xin12m" };
-PNAME(mux_edp_24m_p)		= { "dummy", "xin24m" };
+PNAME(mux_edp_24m_p)		= { "xin24m", "dummy" };
 PNAME(mux_vip_out_p)		= { "vip_src", "xin24m" };
 PNAME(mux_usbphy480m_p)		= { "usbotg_out", "xin24m" };
 PNAME(mux_hsic_usbphy480m_p)	= { "usbotg_out", "dummy" };

-- 
1.9.1

From: zhangqing <redacted>

SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.

Signed-off-by: zhangqing <redacted>
---
 drivers/clk/rockchip/clk-rk3368.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 4885e6b..58ef08b 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c

@@ -353,7 +353,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
 			RK3368_CLKSEL_CON(32), 0,
 			RK3368_CLKGATE_CON(6), 5, GFLAGS),
-	COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
+	COMPOSITE_NODIV(SCLK_SPDIF_8CH, "sclk_spdif_8ch", mux_spdif_8ch_p,
+			CLK_SET_RATE_PARENT,
 			RK3368_CLKSEL_CON(31), 8, 2, MFLAGS,
 			RK3368_CLKGATE_CON(6), 6, GFLAGS),
 	COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,

-- 
1.9.1

From: zhangqing <redacted>

I2S_2CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.

Signed-off-by: zhangqing <redacted>
---
 drivers/clk/rockchip/clk-rk3368.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 58ef08b..5ceb536 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c

@@ -363,7 +363,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
 	COMPOSITE_FRAC(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
 			RK3368_CLKSEL_CON(54), 0,
 			RK3368_CLKGATE_CON(5), 14, GFLAGS),
-	COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p, 0,
+	COMPOSITE_NODIV(SCLK_I2S_2CH, "sclk_i2s_2ch", mux_i2s_2ch_p,
+			CLK_SET_RATE_PARENT,
 			RK3368_CLKSEL_CON(53), 8, 2, MFLAGS,
 			RK3368_CLKGATE_CON(5), 15, GFLAGS),
 

-- 
1.9.1

Hi,

Am Montag, 25. Januar 2016, 08:55:59 schrieb Zhang Qing:

From: zhangqing <redacted>

modify edp_24m parent select bit.
enable CLK_SET_RATE_PARENT flag for spdif_8ch and i2s_2ch.

zhangqing (3):
  clk: rockchip: rk3368: fix edp_24m parent
  clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for
    spdif_8ch
  clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2ch

applied all 3 to my clk branch for 4.6.

I've modified patches 2+3 to keep the line-alingment (= move the CLK_SET_PARENT 
to the line above). In the clock trees I really like to keep the structure 
identical over all clocks (and thus ignore the 80 column limit in parts) to 
make reading the large lists easier, as now everything always is in the same 
place.


Heiko