[PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and print just an information in
case of -ENODEV.

This patch converts the following error message:

   L2C: failed to init: -19

to the following info:

   no L2C controller entry found in the dtb

on boards like odroid-xu4, cortex A7/A15, which don't have
external cache controller.

Signed-off-by: Andi Shyti <redacted>
Reported-by: Krzysztof Kozlowski <redacted>
---
 arch/arm/kernel/irq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 1d45320..abe1ad8 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c

@@ -95,7 +95,9 @@ void __init init_IRQ(void)
 			outer_cache.write_sec = machine_desc->l2c_write_sec;
 		ret = l2x0_of_init(machine_desc->l2c_aux_val,
 				   machine_desc->l2c_aux_mask);
-		if (ret)
+		if (ret == -ENODEV)
+			pr_info("no L2C controller entry found in the dtb\n");
+		else if (ret)
 			pr_err("L2C: failed to init: %d\n", ret);
 	}
 

-- 
2.6.4

On Tue, 2016-01-12 at 15:34 +0900, Andi Shyti wrote:

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and print just an information in
case of -ENODEV.

trivia:

[]

Perhaps this would be more consistent if it was
			pr_info("L2C: no controller entry found in the dtb\n");

+		else if (ret)
?			pr_err("L2C: failed to init: %d\n", ret);
?	}
?

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and print just an information in
case of -ENODEV.

This patch converts the following error message:

   L2C: failed to init: -19

to the following info:

   L2C: no controller entry found in the dtb

on boards like odroid-xu4, cortex A7/A15, which don't have
external cache controller.

Signed-off-by: Andi Shyti <redacted>
Reported-by: Krzysztof Kozlowski <redacted>
---

Thanks Joe,

makes sense!

Andi

 arch/arm/kernel/irq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 1d45320..714b5d6 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c

@@ -95,7 +95,9 @@ void __init init_IRQ(void)
 			outer_cache.write_sec = machine_desc->l2c_write_sec;
 		ret = l2x0_of_init(machine_desc->l2c_aux_val,
 				   machine_desc->l2c_aux_mask);
-		if (ret)
+		if (ret == -ENODEV)
+			pr_info("L2C: no controller entry found in the dtb\n");
+		else if (ret)
 			pr_err("L2C: failed to init: %d\n", ret);
 	}
 

-- 
2.6.4

On 12.01.2016 16:24, Andi Shyti wrote:

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and print just an information in
case of -ENODEV.

This patch converts the following error message:

   L2C: failed to init: -19

to the following info:

   L2C: no controller entry found in the dtb

on boards like odroid-xu4, cortex A7/A15, which don't have
external cache controller.

Signed-off-by: Andi Shyti <redacted>
Reported-by: Krzysztof Kozlowski <redacted>
---

Thanks Joe,

makes sense!

Andi

 arch/arm/kernel/irq.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Works (Odroid XU3, Exynos5422) and looks good for me:

Tested-by: Krzysztof Kozlowski <redacted>
Reviewed-by: Krzysztof Kozlowski <redacted>

Best regards,
Krzysztof

Hello,

On 2016-01-12 08:11, Joe Perches wrote:

On Tue, 2016-01-12 at 15:34 +0900, Andi Shyti wrote:

quoted

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and print just an information in
case of -ENODEV.

trivia:

quoted

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c

[]

quoted

@@ -95,7 +95,9 @@ void __init init_IRQ(void)
  			outer_cache.write_sec = machine_desc->l2c_write_sec;
  		ret = l2x0_of_init(machine_desc->l2c_aux_val,
  				   machine_desc->l2c_aux_mask);
-		if (ret)
+		if (ret == -ENODEV)
+			pr_info("no L2C controller entry found in the dtb\n");

Perhaps this would be more consistent if it was
			pr_info("L2C: no controller entry found in the dtb\n");

Frankly I see no benefit of such message. It still might confuse users 
that there
is something wrong with your DT. When driver initialization fails with 
-ENODEV,
then no message is usually displayed.

quoted

+		else if (ret)
  			pr_err("L2C: failed to init: %d\n", ret);
  	}
  

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and do not print anything in case
l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV.

This patch mutes the following error message:

   L2C: failed to init: -19

on boards like odroid-xu4, cortex A7/A15, which don't have
external cache controller.

Signed-off-by: Andi Shyti <redacted>
Reported-by: Krzysztof Kozlowski <redacted>
Reviewed-by: Krzysztof Kozlowski <redacted>
---
Hi,

here is a second version. An alternative would be to print with
pr_dbg, but then it's a matter of taste.

V1, and V2 print a message in case the l2c dtb entry is not found
(the V2 has a better print rephrase suggested by Joe)

V3 ignores the case of -enodev for l2c and doesn't print anything

Thanks,
Andi

 arch/arm/kernel/irq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 1d45320..ece04a4 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c

@@ -95,7 +95,7 @@ void __init init_IRQ(void)
 			outer_cache.write_sec = machine_desc->l2c_write_sec;
 		ret = l2x0_of_init(machine_desc->l2c_aux_val,
 				   machine_desc->l2c_aux_mask);
-		if (ret)
+		if (ret && ret != -ENODEV)
 			pr_err("L2C: failed to init: %d\n", ret);
 	}
 

-- 
2.6.4

On 12.01.2016 19:11, Andi Shyti wrote:

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and do not print anything in case
l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV.

This patch mutes the following error message:

   L2C: failed to init: -19

on boards like odroid-xu4, cortex A7/A15, which don't have
external cache controller.

Signed-off-by: Andi Shyti <redacted>
Reported-by: Krzysztof Kozlowski <redacted>
Reviewed-by: Krzysztof Kozlowski <redacted>
---
Hi,

here is a second version. An alternative would be to print with
pr_dbg, but then it's a matter of taste.

V1, and V2 print a message in case the l2c dtb entry is not found
(the V2 has a better print rephrase suggested by Joe)

V3 ignores the case of -enodev for l2c and doesn't print anything

Thanks,
Andi

Looks good to me, as v2 did. Works fine:
Tested-by: Krzysztof Kozlowski <redacted>

BR,
KRzysztof

Hello Andi,

On Tue, Jan 12, 2016 at 7:11 AM, Andi Shyti [off-list ref] wrote:

In some architectures the L2 cache controller is integrated in the
processor's block itself and it doesn't use any external cache
controller. This means that an entry in the board's dtb related
to the l2c is not necessary.

Distinguish between error codes and do not print anything in case
l2x0_of_init() doesn't find any L2C DTB entry and returns -ENODEV.

This patch mutes the following error message:

   L2C: failed to init: -19

on boards like odroid-xu4, cortex A7/A15, which don't have
external cache controller.

The patch also looks good to me and makes the error message to go away
in my Exynos5800 Peach Pi.

Reviewed-by: Javier Martinez Canillas <redacted>
Tested-by: Javier Martinez Canillas <redacted>

Best regards,
Javier