[RESEND RFC PATCH 0/2] Add 100MHz integer multiples of cpu freq table for the RK3036

Hi,
  We need the cpu changing freqs capability, and considering that emac
ref which is need 50MHz might is under the APLL, meanwhile, we don't
need too many freqs because it may spend more time to find the correct
freq.
  Therefore, we should add 100MHz integer multiples cpu freqs for
emac.


Xing Zheng (2):
  clk: rockchip: rk3036: Add to 100MHz integer multiples of cpu freq
    table
  ARM: dts: rockchip: Update the cpu freqs table

 arch/arm/boot/dts/rk3036.dtsi     |   13 ++++++++++++-
 drivers/clk/rockchip/clk-rk3036.c |   27 ++++++++++++++++++++++++---
 2 files changed, 36 insertions(+), 4 deletions(-)

-- 
1.7.9.5

We need the cpu changing freqs capability, and considering that emac ref
which is need 50MHz might is under the APLL, meanwhile, we don't need
too many freqs because it may spend more time to find the correct freq.
Therefore, we should add 100MHz integer multiples cpu freqs for emac.

Signed-off-by: Xing Zheng <redacted>
---

 drivers/clk/rockchip/clk-rk3036.c |   27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index bf9dd9b..f60273c 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c

@@ -32,18 +32,22 @@ enum rk3036_plls {
 static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
 	/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
 	RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1600000000, 6, 400, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1500000000, 6, 375, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1400000000, 6, 350, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
+	RK3036_PLL_RATE(1300000000, 6, 325, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
 	RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),

@@ -70,8 +74,12 @@ static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
 	RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
 	RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
 	RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
+	RK3036_PLL_RATE( 400000000, 1, 100, 3, 2, 1, 0),
 	RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
+	RK3036_PLL_RATE( 300000000, 1, 50, 2, 2, 1, 0),
 	RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
+	RK3036_PLL_RATE( 200000000, 1, 50, 3, 2, 1, 0),
+	RK3036_PLL_RATE( 100000000, 6, 400, 4, 4, 1, 0),
 	RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
 	{ /* sentinel */ },
 };

@@ -104,9 +112,22 @@ static struct rockchip_pll_rate_table rk3036_pll_rates[] = {
 	}
 
 static struct rockchip_cpuclk_rate_table rk3036_cpuclk_rates[] __initdata = {
-	RK3036_CPUCLK_RATE(816000000, 4),
-	RK3036_CPUCLK_RATE(600000000, 4),
-	RK3036_CPUCLK_RATE(312000000, 4),
+	RK3036_CPUCLK_RATE(1600000000, 8),
+	RK3036_CPUCLK_RATE(1500000000, 7),
+	RK3036_CPUCLK_RATE(1400000000, 7),
+	RK3036_CPUCLK_RATE(1300000000, 6),
+	RK3036_CPUCLK_RATE(1200000000, 6),
+	RK3036_CPUCLK_RATE(1100000000, 5),
+	RK3036_CPUCLK_RATE(1000000000, 5),
+	RK3036_CPUCLK_RATE( 900000000, 4),
+	RK3036_CPUCLK_RATE( 800000000, 4),
+	RK3036_CPUCLK_RATE( 700000000, 3),
+	RK3036_CPUCLK_RATE( 600000000, 3),
+	RK3036_CPUCLK_RATE( 500000000, 3),
+	RK3036_CPUCLK_RATE( 400000000, 3),
+	RK3036_CPUCLK_RATE( 300000000, 2),
+	RK3036_CPUCLK_RATE( 200000000, 1),
+	RK3036_CPUCLK_RATE( 100000000, 1),
 };
 
 static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {

-- 
1.7.9.5

Actually, we need more cpu freqs which are 50MHz integer multiples.

Signed-off-by: Xing Zheng <redacted>
---

 arch/arm/boot/dts/rk3036.dtsi |   13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 1cb5877..1a773eb 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi

@@ -79,7 +79,18 @@
 			resets = <&cru SRST_CORE0>;
 			operating-points = <
 				/* KHz    uV */
-				 816000 1000000
+				1200000 1200000
+				1100000 1200000
+				1000000 1200000
+				 900000 1200000
+				 800000 1200000
+				 700000 1200000
+				 600000 1200000
+				 500000 1200000
+				 400000 1200000
+				 300000 1200000
+				 200000 1200000
+				 100000 1200000
 			>;
 			clock-latency = <40000>;
 			clocks = <&cru ARMCLK>;

-- 
1.7.9.5

Hi Xing,

Am Freitag, 8. Januar 2016, 19:31:38 schrieb Xing Zheng:

what about reducing the voltage as well?

From rk3288-specific discussions I remember that reducing the frequency 

without touching the voltage, didn't really save so much energy.
And it looks like it was running 816MHz at 1.0V just fine as well.

I guess you should find out which voltages are really necessary for each 
step.


Heiko

Hi Heiko,

On 2016?01?09? 03:16, Heiko Stuebner wrote:

Hi Xing,

Am Freitag, 8. Januar 2016, 19:31:38 schrieb Xing Zheng:

quoted

Actually, we need more cpu freqs which are 50MHz integer multiples.

Signed-off-by: Xing Zheng <redacted>
---

  arch/arm/boot/dts/rk3036.dtsi |   13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 1cb5877..1a773eb 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi

@@ -79,7 +79,18 @@
  			resets = <&cru SRST_CORE0>;
  			operating-points = <
  				/* KHz    uV */
-				 816000 1000000
+				1200000 1200000
+				1100000 1200000
+				1000000 1200000
+				 900000 1200000
+				 800000 1200000
+				 700000 1200000
+				 600000 1200000
+				 500000 1200000
+				 400000 1200000
+				 300000 1200000
+				 200000 1200000
+				 100000 1200000

what about reducing the voltage as well?

quoted

From rk3288-specific discussions I remember that reducing the frequency

without touching the voltage, didn't really save so much energy.
And it looks like it was running 816MHz at 1.0V just fine as well.

I guess you should find out which voltages are really necessary for each
step.


Heiko

Thank you for your comments. :-)

Yes, these patches currently still in draft stage. Modify the frequency 
of 816MHz is for mac apll patch can be FROMLIST for Kylin Board,
and will work cpu frequency table as a start.

We know you want to set the appropriate frequency of different batches 
of The RK3036 SoCs take some time,so I just tested a fixed
high voltage 1.2v on my evb board, the frequency of the voltage to 
ensure that we can work needed.
We'll start work dynamically adjust the voltage.

Thanks.

- Xing Zheng