[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

Subsystems: common clk framework, samsung soc clock drivers, the rest

STALE4455d

7 messages, 4 authors, 2014-06-30 · open the first message on its own page

[PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

From: Rahul Sharma <hidden>
Date: 2014-06-19 05:47:16 

Change bit from 2 to 9 for tv (mixer) sysmmu clock.

Signed-off-by: Rahul Sharma <redacted>
---
Based on Kukjin's for-next branch.

 drivers/clk/samsung/clk-exynos5250.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1fad4c5..184f642 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
 	GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
 	GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
-			GATE_IP_DISP1, 2, 0, 0),
+			GATE_IP_DISP1, 9, 0, 0),
 	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
 			GATE_IP_DISP1, 8, 0, 0),
 	GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
-- 
1.7.9.5

Re: [PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

From: Sachin Kamat <hidden>
Date: 2014-06-19 06:05:12 

On Thu, Jun 19, 2014 at 11:17 AM, Rahul Sharma [off-list ref] wrote:
quoted hunk
Change bit from 2 to 9 for tv (mixer) sysmmu clock.

Signed-off-by: Rahul Sharma <redacted>
---
Based on Kukjin's for-next branch.

 drivers/clk/samsung/clk-exynos5250.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1fad4c5..184f642 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
        GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
        GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
        GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
-                       GATE_IP_DISP1, 2, 0, 0),
+                       GATE_IP_DISP1, 9, 0, 0),
SysMMU TV corresponds to bit 9 as per user manual of 5250.
Reviewed-by: Sachin Kamat <redacted>

Re: [PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

From: Rahul Sharma <hidden>
Date: 2014-06-25 11:22:41 

Hi Kukjin,

Please take this fix in your tree.

Regards,
Rahul Sharma

On 19 June 2014 11:35, Sachin Kamat [off-list ref] wrote:
On Thu, Jun 19, 2014 at 11:17 AM, Rahul Sharma [off-list ref] wrote:
quoted
Change bit from 2 to 9 for tv (mixer) sysmmu clock.

Signed-off-by: Rahul Sharma <redacted>
---
Based on Kukjin's for-next branch.

 drivers/clk/samsung/clk-exynos5250.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1fad4c5..184f642 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
        GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
        GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
        GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
-                       GATE_IP_DISP1, 2, 0, 0),
+                       GATE_IP_DISP1, 9, 0, 0),
SysMMU TV corresponds to bit 9 as per user manual of 5250.
Reviewed-by: Sachin Kamat <redacted>

Re: [PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

From: Tomasz Figa <hidden>
Date: 2014-06-25 11:24:04 

Hi Rahul,

On 25.06.2014 13:22, Rahul Sharma wrote:
Hi Kukjin,

Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll apply it when about
to send fixes pull request to Mike.

Best regards,
Tomasz

RE: [PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

From: Kukjin Kim <hidden>
Date: 2014-06-25 11:26:04 

Tomasz Figa wrote:
Hi Rahul,

On 25.06.2014 13:22, Rahul Sharma wrote:
quoted
Hi Kukjin,

Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll apply it when about
to send fixes pull request to Mike.
Yes, I also checked the datasheet and this change is correct.

If you want, please add my ack on the patch.

Thanks,
Kukjin

Re: [PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

From: Rahul Sharma <hidden>
Date: 2014-06-25 12:57:10 

Sure Tomasz, Kukjin.
Thanks for the update.

Regards.

On 25 June 2014 16:56, Kukjin Kim [off-list ref] wrote:
Tomasz Figa wrote:
quoted
Hi Rahul,

On 25.06.2014 13:22, Rahul Sharma wrote:
quoted
Hi Kukjin,

Please take this fix in your tree.
This is a patch for Samsung clock drivers, so I'll apply it when about
to send fixes pull request to Mike.
Yes, I also checked the datasheet and this change is correct.

If you want, please add my ack on the patch.

Thanks,
Kukjin


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Re: [PATCH] clk/exynos5250: fix bit number for tv sysmmu clock

From: Tomasz Figa <hidden>
Date: 2014-06-30 13:49:47 

On 19.06.2014 07:47, Rahul Sharma wrote:
quoted hunk
Change bit from 2 to 9 for tv (mixer) sysmmu clock.

Signed-off-by: Rahul Sharma <redacted>
---
Based on Kukjin's for-next branch.

 drivers/clk/samsung/clk-exynos5250.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1fad4c5..184f642 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
 	GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
 	GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
 	GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
-			GATE_IP_DISP1, 2, 0, 0),
+			GATE_IP_DISP1, 9, 0, 0),
 	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
 			GATE_IP_DISP1, 8, 0, 0),
 	GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
Applied as a fix for 3.16.

Best regards,
Tomasz
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