[PATCH] gic: change access of gicc_ctrl register to read modify write.
From: Feng Kan <hidden>
Date: 2014-02-14 01:52:49
Also in:
lkml
Subsystem:
arm generic interrupt controller drivers, irqchip drivers, the rest · Maintainers:
Marc Zyngier, Thomas Gleixner, Linus Torvalds
This change is made to preserve the GIC v2 releated bits in the GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec). The original code only set the enable/disable group bit in this register. This code will preserve all other bits configured by the bootload except the enable/disable bit. The main reason for this change is to allow the bypass bits specified in the v2 spec to remain untouched by the current GIC code. In the X-Gene platform, the bypass functionality is not used and bypass must be disabled at all time. Signed-off-by: Vinayak Kale <redacted> Acked-by: Anup Patel <redacted> Signed-off-by: Feng Kan <redacted> --- drivers/irqchip/irq-gic.c | 19 ++++++++++++++++--- 1 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 341c601..4a52a97e2 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c@@ -418,6 +418,7 @@ static void gic_cpu_init(struct gic_chip_data *gic) void __iomem *dist_base = gic_data_dist_base(gic); void __iomem *base = gic_data_cpu_base(gic); unsigned int cpu_mask, cpu = smp_processor_id(); + unsigned int ctrl_mask; int i; /*
@@ -449,13 +450,21 @@ static void gic_cpu_init(struct gic_chip_data *gic) writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); - writel_relaxed(1, base + GIC_CPU_CTRL); + + ctrl_mask = readl(base + GIC_CPU_CTRL); + ctrl_mask |= 0x1; + writel_relaxed(ctrl_mask, base + GIC_CPU_CTRL); } void gic_cpu_if_down(void) { + unsigned int ctrl_mask; + void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); - writel_relaxed(0, cpu_base + GIC_CPU_CTRL); + + ctrl_mask = readl(base + GIC_CPU_CTRL); + ctrl_mask &= 0xfffffffe; + writel_relaxed(ctrl_mask, cpu_base + GIC_CPU_CTRL); } #ifdef CONFIG_CPU_PM
@@ -566,6 +575,7 @@ static void gic_cpu_restore(unsigned int gic_nr) { int i; u32 *ptr; + unsigned int ctrl_mask; void __iomem *dist_base; void __iomem *cpu_base;
@@ -590,7 +600,10 @@ static void gic_cpu_restore(unsigned int gic_nr) writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); - writel_relaxed(1, cpu_base + GIC_CPU_CTRL); + + ctrl_mask = readl(base + GIC_CPU_CTRL); + ctrl_mask |= 0x1; + writel_relaxed(ctrl_mask, cpu_base + GIC_CPU_CTRL); } static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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1.7.6.1