[PATCH V3 0/4] ARM: tegra: Enable SLINK controller driver

This series modify the dts file to add the slink addresses,
make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and 
enable slink controller defconfig.

Changes from V1: 
- Remove changes from clock tables.
- Make the dma req dt property name to nvidia,dma-request-selector.
- change the spi max frequency prop to spi-max-frequency.

Changes from V2:
- make node name to spi.
- get rid of iomap.h.

Laxman Dewangan (4):
  ARM: tegra: dts: add slink controller dt entry
  ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt
  ARM: tegra: dts: cardhu: enable SLINK4
  ARM: tegra: config: enable spi driver for Tegra SLINK controller

 arch/arm/boot/dts/tegra20.dtsi         |   41 ++++++++++++++++++++++
 arch/arm/boot/dts/tegra30-cardhu.dtsi  |    5 +++
 arch/arm/boot/dts/tegra30.dtsi         |   60 ++++++++++++++++++++++++++++++++
 arch/arm/configs/tegra_defconfig       |    2 +-
 arch/arm/mach-tegra/board-dt-tegra20.c |    8 ++++
 arch/arm/mach-tegra/board-dt-tegra30.c |   12 ++++++
 6 files changed, 127 insertions(+), 1 deletions(-)

Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30
board dt files.
Set the parent clock of slink controller to PLLP and configure
clock to 100MHz.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- Revert the changes in clock table to get the driver name.

Changes from V2:
- Get rid of the iomap.h

 arch/arm/mach-tegra/board-dt-tegra20.c |    8 ++++++++
 arch/arm/mach-tegra/board-dt-tegra30.c |   12 ++++++++++++
 2 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 2053f74..5a19589 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c

@@ -90,6 +90,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 		       &tegra_ehci3_pdata),
 	OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
 	{}
 };
 

@@ -109,6 +113,10 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
 	{ "sdmmc1",	"pll_p",	48000000,	false},
 	{ "sdmmc3",	"pll_p",	48000000,	false},
 	{ "sdmmc4",	"pll_p",	48000000,	false},
+	{ "sbc1",	"pll_p",	100000000,	false },
+	{ "sbc2",	"pll_p",	100000000,	false },
+	{ "sbc3",	"pll_p",	100000000,	false },
+	{ "sbc4",	"pll_p",	100000000,	false },
 	{ NULL,		NULL,		0,		0},
 };
 

diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 9e6f79a..b26cfef 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c

@@ -52,6 +52,12 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
 	OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
 	OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
+	OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
 	{}
 };
 

@@ -71,6 +77,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
 	{ "sdmmc1",	"pll_p",	48000000,	false},
 	{ "sdmmc3",	"pll_p",	48000000,	false},
 	{ "sdmmc4",	"pll_p",	48000000,	false},
+	{ "sbc1",	"pll_p",	100000000,	false},
+	{ "sbc2",	"pll_p",	100000000,	false},
+	{ "sbc3",	"pll_p",	100000000,	false},
+	{ "sbc4",	"pll_p",	100000000,	false},
+	{ "sbc5",	"pll_p",	100000000,	false},
+	{ "sbc6",	"pll_p",	100000000,	false},
 	{ NULL,		NULL,		0,		0},
 };
 

-- 
1.7.1.1

Enable SLINK4 in Tegra30 based platform Cardhu.
Setting maximum spi frequency to 25MHz.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- rename the max freq prop to spi-max-frequency

Changes from V2:
- make node name to spi@

 arch/arm/boot/dts/tegra30-cardhu.dtsi |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index b245e6c..700f0a3 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi

@@ -275,6 +275,11 @@
 		};
 	};
 
+	spi at 7000da00 {
+		status = "okay";
+		spi-max-frequency = <25000000>;
+	};
+
 	ahub {
 		i2s at 70080400 {
 			status = "okay";

-- 
1.7.1.1

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
No change from V1 and V2.

 arch/arm/configs/tegra_defconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index fb29680..60e1b2e 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig

@@ -117,7 +117,7 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
-CONFIG_SPI_TEGRA=y
+CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y

-- 
1.7.1.1

Add slink controller details in the dts file of
Tegra20 and Tegra30.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
-rename the dma request prop to nvidia,dma-request-selector.

Changes from V2:
- Make node name as spi at .

 arch/arm/boot/dts/tegra20.dtsi |   41 +++++++++++++++++++++++++++
 arch/arm/boot/dts/tegra30.dtsi |   60 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 101 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 6934bca..ecd3b4f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi

@@ -186,6 +186,47 @@
 		status = "disabled";
 	};
 
+	spi at 7000d400 {
+
+		compatible = "nvidia,tegra20-slink";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi at 7000d600 {
+		compatible = "nvidia,tegra20-slink";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi at 7000d800 {
+		compatible = "nvidia,tegra20-slink";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi at 7000da00 {
+		compatible = "nvidia,tegra20-slink";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	pmc {
 		compatible = "nvidia,tegra20-pmc";
 		reg = <0x7000e400 0x400>;

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 81f5df4..ab6cfb0 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi

@@ -191,6 +191,66 @@
 		status = "disabled";
 	};
 
+	spi at 7000d400 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d400 0x200>;
+		interrupts = <0 59 0x04>;
+		nvidia,dma-request-selector = <&apbdma 15>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi at 7000d600 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d600 0x200>;
+		interrupts = <0 82 0x04>;
+		nvidia,dma-request-selector = <&apbdma 16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi at 7000d800 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000d480 0x200>;
+		interrupts = <0 83 0x04>;
+		nvidia,dma-request-selector = <&apbdma 17>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi at 7000da00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000da00 0x200>;
+		interrupts = <0 93 0x04>;
+		nvidia,dma-request-selector = <&apbdma 18>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi at 7000dc00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000dc00 0x200>;
+		interrupts = <0 94 0x04>;
+		nvidia,dma-request-selector = <&apbdma 27>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	spi at 7000de00 {
+		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+		reg = <0x7000de00 0x200>;
+		interrupts = <0 79 0x04>;
+		nvidia,dma-request-selector = <&apbdma 28>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	pmc {
 		compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
 		reg = <0x7000e400 0x400>;

-- 
1.7.1.1

On 10/30/2012 01:05 AM, Laxman Dewangan wrote:

This series modify the dts file to add the slink addresses,
make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and 
enable slink controller defconfig.

This series only instantiates the SPI controller, and not any SPI
devices. I tried to solve this:

However, this didn't work. Has the driver been tested? I'm seeing the
exact same problems I saw with the old driver, namely that the SPI flash
chip can't be identified; I think the ID bytes are read back as 0, and
hence drivers/mtd/devices/m25p80.c falls back to identifying the device
as mr25h256. Attempting to hexdump -C /dev/mtd0 gives me 32K of zeros,
whereas the device is 4M and full of non-zero data according to U-Boot.

Do you know what the problem is here? Can you please update the patch
series so that the SPI flash is instantiated and works correctly?

On Wednesday 31 October 2012 01:59 AM, Stephen Warren wrote:

On 10/30/2012 01:05 AM, Laxman Dewangan wrote:

quoted

This series modify the dts file to add the slink addresses,
make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and
enable slink controller defconfig.

This series only instantiates the SPI controller, and not any SPI
devices. I tried to solve this:

quoted

diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 700f0a3..3689853 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi

@@ -278,6 +278,11 @@
         spi at 7000da00 {
                 status = "okay";
                 spi-max-frequency =<25000000>;
+               flash at 0 {
+                       reg =<0>;
+                       compatible = "atmel,at25df321a";
+                       spi-max-frequency =<25000000>;
+               };
         };

         ahub {

However, this didn't work. Has the driver been tested? I'm seeing the
exact same problems I saw with the old driver, namely that the SPI flash
chip can't be identified; I think the ID bytes are read back as 0, and
hence drivers/mtd/devices/m25p80.c falls back to identifying the device
as mr25h256. Attempting to hexdump -C /dev/mtd0 gives me 32K of zeros,
whereas the device is 4M and full of non-zero data according to U-Boot.

Do you know what the problem is here? Can you please update the patch
series so that the SPI flash is instantiated and works correctly?

I will send the new patch series for taking care of the issue.

In Cardhu, there is 2 different type of flash, Winbond and Atmel.
There is hw rework require in Cardhu A02 to enable the serial flash and 
it is already taken care in Cardhu A04. I will forward the hw rework 
details to you in internal mail communication.

Also Serial flash is in CS1, not in CS0. So even if you have hw rework, 
above change will not work.

I had tested on different way earlier (dynamic allocating master for 
serial flash) and also tested on above method.
For this I enable MTD, MTD_CHAR and MTD_M25P80.
Debug prints as:
[    1.279424] m25p_probe
[    1.282536] m25p80 spi32766.1: w25q32 (4096 Kbytes)
[    1.287418] mtd .name = spi32766.1, .size = 0x400000 (4MiB) 
.erasesize = 0x00
001000 (4KiB) .numeraseregions = 0
[    1.298120] m25p_probe() returns 0

On 10/31/2012 02:51 AM, Laxman Dewangan wrote:

On Wednesday 31 October 2012 01:59 AM, Stephen Warren wrote:

quoted

On 10/30/2012 01:05 AM, Laxman Dewangan wrote:

quoted

This series modify the dts file to add the slink addresses,
make AUXDATA in board dt files, enable slink4 for tegra30-cardhu and
enable slink controller defconfig.

This series only instantiates the SPI controller, and not any SPI
devices. I tried to solve this:

quoted

diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi

b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 700f0a3..3689853 100644

--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi

@@ -278,6 +278,11 @@
         spi at 7000da00 {
                 status = "okay";
                 spi-max-frequency =<25000000>;
+               flash at 0 {
+                       reg =<0>;
+                       compatible = "atmel,at25df321a";
+                       spi-max-frequency =<25000000>;
+               };
         };

         ahub {

However, this didn't work. Has the driver been tested? I'm seeing the
exact same problems I saw with the old driver, namely that the SPI flash
chip can't be identified; I think the ID bytes are read back as 0, and
hence drivers/mtd/devices/m25p80.c falls back to identifying the device
as mr25h256. Attempting to hexdump -C /dev/mtd0 gives me 32K of zeros,
whereas the device is 4M and full of non-zero data according to U-Boot.

Do you know what the problem is here? Can you please update the patch
series so that the SPI flash is instantiated and works correctly?

I will send the new patch series for taking care of the issue.

In Cardhu, there is 2 different type of flash, Winbond and Atmel.
There is hw rework require in Cardhu A02 to enable the serial flash and
it is already taken care in Cardhu A04. I will forward the hw rework
details to you in internal mail communication.

U-Boot appears able to identify the flash chip on my board:

SF: Detected AT25DF321A with page size 256, total 4 MiB

So I guess I have the rework.

Also Serial flash is in CS1, not in CS0. So even if you have hw rework,
above change will not work.

Presumably that simply requires changing from:

              flash at 0 {
                      reg = <0>;

to:

              flash at 1 {
                      reg = <1>;

Aha, indeed that does appear to solve the issue; I can see the U-Boot
environment block when I run "hexdump -C /dev/mtd0" now.

I had forgotten about this from when I tested the older SPI driver that
we ripped out; I had at least compared the registers between U-Boot and
the kernel with that driver, so I'm pretty sure I didn't make that
mistake with the old driver.

So, I'll apply your patch series, and send one to add the flash device
to the Cardhu .dts.

On Wednesday 31 October 2012 09:36 PM, Stephen Warren wrote:

On 10/31/2012 02:51 AM, Laxman Dewangan wrote:

I had forgotten about this from when I tested the older SPI driver that
we ripped out; I had at least compared the registers between U-Boot and
the kernel with that driver, so I'm pretty sure I didn't make that
mistake with the old driver.

So, I'll apply your patch series, and send one to add the flash device
to the Cardhu .dts.

Great  to hear that the spi driver work for you now.

Thanks,
Laxman