[PATCH] clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

Subsystems: common clk framework, the rest

STALE5176d

6 messages, 4 authors, 2012-07-05 · open the first message on its own page

[PATCH] clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

From: Lauri Hintsala <hidden>
Date: 2012-07-04 10:49:54

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand
the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

Signed-off-by: Lauri Hintsala <redacted>
---
 drivers/clk/mxs/clk-imx28.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 2826a26..0097c3a 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c

@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
 
 	/*
 	 * 480 MHz seems too high to be ssp clock source directly,
-	 * so set frac0 to get a 288 MHz ref_io0.
+	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 	 */
 	val = readl_relaxed(FRAC0);
-	val &= ~(0x3f << BP_FRAC0_IO0FRAC);
-	val |= 30 << BP_FRAC0_IO0FRAC;
+	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 	writel_relaxed(val, FRAC0);
 }

-- 
1.7.9.5

[PATCH] clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

From: Shawn Guo <hidden>
Date: 2012-07-04 13:35:56

On Wed, Jul 04, 2012 at 01:49:54PM +0300, Lauri Hintsala wrote:

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand
the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

The patch looks okay.  Just to confirm that you are running SSP2&SSP3
into the same frequency problem that we had with SSP0&SSP1?  I never
got a board to verify that for SSP2&SSP3.

Regards,
Shawn

quoted hunk

Signed-off-by: Lauri Hintsala <redacted>
---
 drivers/clk/mxs/clk-imx28.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 2826a26..0097c3a 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c

@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
 
 	/*
 	 * 480 MHz seems too high to be ssp clock source directly,
-	 * so set frac0 to get a 288 MHz ref_io0.
+	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 	 */
 	val = readl_relaxed(FRAC0);
-	val &= ~(0x3f << BP_FRAC0_IO0FRAC);
-	val |= 30 << BP_FRAC0_IO0FRAC;
+	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 	writel_relaxed(val, FRAC0);
 }

-- 
1.7.9.5

[PATCH] clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

From: Lauri Hintsala <hidden>
Date: 2012-07-04 14:02:30

On 07/04/2012 04:35 PM, Shawn Guo wrote:

On Wed, Jul 04, 2012 at 01:49:54PM +0300, Lauri Hintsala wrote:

quoted

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand
the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

The patch looks okay.  Just to confirm that you are running SSP2&SSP3
into the same frequency problem that we had with SSP0&SSP1?  I never
got a board to verify that for SSP2&SSP3.

SDIO device connected to SSP2 is not detect without this change. I don't 
know what is the history of ref_io0 frequency change but the same change 
is needed for ref_io1 to get SSP2 to work on our imx28 based module.

Regards,
Lauri

[PATCH] clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

From: marex@denx.de (Marek Vasut)
Date: 2012-07-04 16:23:27

Dear Shawn Guo,

On Wed, Jul 04, 2012 at 01:49:54PM +0300, Lauri Hintsala wrote:

quoted

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand
the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

The patch looks okay.  Just to confirm that you are running SSP2&SSP3
into the same frequency problem that we had with SSP0&SSP1?  I never
got a board to verify that for SSP2&SSP3.

What problem is that? I've been running the SPI driver against two types of SPI 
flashes on SSP2 without trouble ...

Regards,
Shawn

quoted

Signed-off-by: Lauri Hintsala <redacted>
---

 drivers/clk/mxs/clk-imx28.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 2826a26..0097c3a 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c

@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)

 	/*
 	
 	 * 480 MHz seems too high to be ssp clock source directly,

-	 * so set frac0 to get a 288 MHz ref_io0.
+	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.

 	 */
 	
 	val = readl_relaxed(FRAC0);

-	val &= ~(0x3f << BP_FRAC0_IO0FRAC);
-	val |= 30 << BP_FRAC0_IO0FRAC;
+	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);

 	writel_relaxed(val, FRAC0);
 
 }

Best regards,
Marek Vasut

[PATCH] clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

From: festevam@gmail.com (Fabio Estevam)
Date: 2012-07-04 16:39:45

On Wed, Jul 4, 2012 at 1:23 PM, Marek Vasut [off-list ref] wrote:

What problem is that? I've been running the SPI driver against two types of SPI
flashes on SSP2 without trouble ...

I guess Shawn is referring to this:
http://www.spinics.net/lists/arm-kernel/msg180725.html

[PATCH] clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3

From: Shawn Guo <hidden>
Date: 2012-07-05 03:06:56

On Wed, Jul 04, 2012 at 01:49:54PM +0300, Lauri Hintsala wrote:

SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand
the frequency fix for ref_io1 to get SSP2 and SSP3 to work.

Signed-off-by: Lauri Hintsala <redacted>

Applied, thanks.

quoted hunk

---
 drivers/clk/mxs/clk-imx28.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 2826a26..0097c3a 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c

@@ -112,11 +112,11 @@ static void __init clk_misc_init(void)
 
 	/*
 	 * 480 MHz seems too high to be ssp clock source directly,
-	 * so set frac0 to get a 288 MHz ref_io0.
+	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.
 	 */
 	val = readl_relaxed(FRAC0);
-	val &= ~(0x3f << BP_FRAC0_IO0FRAC);
-	val |= 30 << BP_FRAC0_IO0FRAC;
+	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));
+	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);
 	writel_relaxed(val, FRAC0);
 }

-- 
1.7.9.5

`h`	back out one level
`j`	next message in thread
`k`	previous message in thread
`l`	drill in
`Esc`	close help / fold thread tree
`?`	toggle this help