From: Thomas Abraham <hidden> Date: 2012-07-12 12:40:43
This patch series adds device tree support for Synopsis Designware Mobile
Storage Host Controller.
The first patch converts the copy of controller device instance into a
reference. This is need to allow device resource management api to correctly
manage the resources allocated by the driver. The second patch fixes the
incorrect abort of the probe in case a slot initialization fails. This is
fixed by allowing as many slots to be initialized successfully and failing
only if there are no slots that were initialized.
The third patch adds clock lookup in the driver and this is optional. Platforms
that do not need any clock gating and control for the dw_mmc controllers will
not be affected with this change. The fourth patch adds a quirk to notify the
controller about the absence of the write protect line.
The fifth patch adds device tree based discovery support for the dw_mmc driver.
The sixth patch add Samsung Exynos5250 specific extentions to the driver.
This patchset is based on Samsung kernel tree's for-next branch with the
mmc tree's mmc-next branch merged.
Thomas Abraham (6):
mmc: dw_mmc: convert copy of struct device in struct dw_mci to a reference
mmc: dw_mmc: allow probe to succeed even if one slot is initialized
mmc: dw_mmc: lookup for optional biu and ciu clocks
mmc: dw_mmc: add quirk to indicate missing write protect line
mmc: dw_mmc: add device tree support
mmc: dw_mmc: add samsung exynos5250 specific extentions
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 144 ++++++++
drivers/mmc/host/dw_mmc-pci.c | 2 +-
drivers/mmc/host/dw_mmc-pltfm.c | 41 +++-
drivers/mmc/host/dw_mmc.c | 364 +++++++++++++++++---
drivers/mmc/host/dw_mmc.h | 23 ++
include/linux/mmc/dw_mmc.h | 17 +-
6 files changed, 538 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
From: Thomas Abraham <hidden> Date: 2012-07-12 12:40:49
The 'struct dw_mci' maintains a copy of the pdev->dev instance instead of
maintaining a reference to that 'struct device' instance. Any resource
allocated using the device resource management kernel API with the instance
of 'struct device' in 'struct dw_mci' is then incorrect. Fix this by
converting the copy of 'struct device' in 'struct dw_mci' to a reference.
Signed-off-by: Thomas Abraham <redacted>
---
drivers/mmc/host/dw_mmc-pci.c | 2 +-
drivers/mmc/host/dw_mmc-pltfm.c | 2 +-
drivers/mmc/host/dw_mmc.c | 56 +++++++++++++++++++-------------------
include/linux/mmc/dw_mmc.h | 2 +-
4 files changed, 31 insertions(+), 31 deletions(-)
@@ -414,13 +414,13 @@ static int dw_mci_idmac_init(struct dw_mci *host)dma_support=(mci_readl(host,HCON)>>16)&0x3;if(!dma_support||dma_support>2){-dev_err(&host->dev,+dev_err(host->dev,"Host Controller does not support IDMA Tx.\n");host->dma_ops=NULL;return-ENODEV;}-dev_info(&host->dev,"Using internal DMA controller.\n");+dev_info(host->dev,"Using internal DMA controller.\n");/* Forward link the descriptor list */for(i=0,p=host->sg_cpu;i<host->ring_size-1;i++,p++)
@@ -476,7 +476,7 @@ static int dw_mci_pre_dma_transfer(struct dw_mci *host,return-EINVAL;}-sg_len=dma_map_sg(&host->dev,+sg_len=dma_map_sg(host->dev,data->sg,data->sg_len,dw_mci_get_dma_dir(data));
@@ -1765,7 +1765,7 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)structmmc_host*mmc;structdw_mci_slot*slot;-mmc=mmc_alloc_host(sizeof(structdw_mci_slot),&host->dev);+mmc=mmc_alloc_host(sizeof(structdw_mci_slot),host->dev);if(!mmc)return-ENOMEM;
@@ -1877,10 +1877,10 @@ static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)staticvoiddw_mci_init_dma(structdw_mci*host){/* Alloc memory for sg translation */-host->sg_cpu=dma_alloc_coherent(&host->dev,PAGE_SIZE,+host->sg_cpu=dma_alloc_coherent(host->dev,PAGE_SIZE,&host->sg_dma,GFP_KERNEL);if(!host->sg_cpu){-dev_err(&host->dev,"%s: could not alloc DMA memory\n",+dev_err(host->dev,"%s: could not alloc DMA memory\n",__func__);gotono_dma;}
@@ -1896,12 +1896,12 @@ static void dw_mci_init_dma(struct dw_mci *host)if(host->dma_ops->init&&host->dma_ops->start&&host->dma_ops->stop&&host->dma_ops->cleanup){if(host->dma_ops->init(host)){-dev_err(&host->dev,"%s: Unable to initialize "+dev_err(host->dev,"%s: Unable to initialize ""DMA Controller.\n",__func__);gotono_dma;}}else{-dev_err(&host->dev,"DMA initialization not found.\n");+dev_err(host->dev,"DMA initialization not found.\n");gotono_dma;}
@@ -1909,7 +1909,7 @@ static void dw_mci_init_dma(struct dw_mci *host)return;no_dma:-dev_info(&host->dev,"Using PIO mode.\n");+dev_info(host->dev,"Using PIO mode.\n");host->use_dma=0;return;}
@@ -1941,19 +1941,19 @@ int dw_mci_probe(struct dw_mci *host)u32fifo_size;if(!host->pdata||!host->pdata->init){-dev_err(&host->dev,+dev_err(host->dev,"Platform data must supply init function\n");return-ENODEV;}if(!host->pdata->select_slot&&host->pdata->num_slots>1){-dev_err(&host->dev,+dev_err(host->dev,"Platform data must supply select_slot function\n");return-ENODEV;}if(!host->pdata->bus_hz){-dev_err(&host->dev,+dev_err(host->dev,"Platform data must supply bus speed\n");return-ENODEV;}
@@ -1991,7 +1991,7 @@ int dw_mci_probe(struct dw_mci *host)}/* Reset all blocks */-if(!mci_wait_reset(&host->dev,host))+if(!mci_wait_reset(host->dev,host))return-ENODEV;host->dma_ops=host->pdata->dma_ops;
@@ -2058,7 +2058,7 @@ int dw_mci_probe(struct dw_mci *host)*Needtochecktheversion-idandsetdata-offsetforDATAregister.*/host->verid=SDMMC_GET_VERID(mci_readl(host,VERID));-dev_info(&host->dev,"Version ID is %04x\n",host->verid);+dev_info(host->dev,"Version ID is %04x\n",host->verid);if(host->verid<DW_MMC_240A)host->data_offset=DATA_OFFSET;
@@ -2075,12 +2075,12 @@ int dw_mci_probe(struct dw_mci *host)DW_MCI_ERROR_FLAGS|SDMMC_INT_CD);mci_writel(host,CTRL,SDMMC_CTRL_INT_ENABLE);/* Enable mci interrupt */-dev_info(&host->dev,"DW MMC controller at irq %d, "+dev_info(host->dev,"DW MMC controller at irq %d, ""%d bit host data width, ""%u deep fifo\n",host->irq,width,fifo_size);if(host->quirks&DW_MCI_QUIRK_IDMAC_DTO)-dev_info(&host->dev,"Internal DMAC interrupt fix enabled.\n");+dev_info(host->dev,"Internal DMAC interrupt fix enabled.\n");return0;
From: Thomas Abraham <hidden> Date: 2012-07-12 12:40:55
If the write protect pad of the controller is not connected to the write
protect pin of the slot, the driver should be notified of this condition
so that incorrect check for write protection by reading the WRTORT
register can avoided. The get_ro platform callback can be used for in
such cases, but with device tree support enabled, such platform callbacks
cannot be supported.
Add a new quirk for notifying the driver about the missing write protect
line so the driver can assume that the card write protection is disabled.
Signed-off-by: Thomas Abraham <redacted>
Acked-by: Will Newton <redacted>
---
drivers/mmc/host/dw_mmc.c | 4 +++-
include/linux/mmc/dw_mmc.h | 3 ++-
2 files changed, 5 insertions(+), 2 deletions(-)
From: Thomas Abraham <hidden> Date: 2012-07-12 12:40:59
The instantiation of the Synopsis Designware controller on Exynos5250
include extension for SDR and DDR specific tx/rx phase shift timing
and CIU internal divider. In addition to that, the option to skip the
command hold stage is also introduced. Add support for these Exynos5250
specfic extenstions.
Signed-off-by: Abhilash Kesavan <redacted>
Signed-off-by: Thomas Abraham <redacted>
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 38 ++++++++++++++++++-
drivers/mmc/host/dw_mmc-pltfm.c | 15 +++++++
drivers/mmc/host/dw_mmc.c | 40 +++++++++++++++++++-
drivers/mmc/host/dw_mmc.h | 14 +++++++
include/linux/mmc/dw_mmc.h | 6 +++
5 files changed, 110 insertions(+), 3 deletions(-)
@@ -7,6 +7,8 @@ Required Properties: * compatible: should be one of the following - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.+ - samsung,exynos5250-dw-mshc: for controllers with Samsung+ Exynos5250 specific extentions. * reg: physical base address of the dw-mshc controller and size of its memory region.
@@ -74,13 +76,45 @@ Aliases: the following format 'mshc{n}' where n is a unique number for the alias.+Samsung Exynos4/5 specific properties:++Some of the variants of Exynos4 (such as Exynos4412) and Exynos5 SoC's+includes few extensions to the Synopsis Designware Mobile Storage Host+Controller. The following properties are used to describe those extensions.++* samsung,dw-mshc-sdr-timing: Specifies the value of CUI clock divider, CIU+ clock phase shift value in transmit mode and CIU clock phase shift value in+ receive mode for single data rate mode operation. Refer notes of the valid+ values below.++* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock divider, CIU+ clock phase shift value in transmit mode and CIU clock phase shift value in+ receive mode for double data rate mode operation. Refer notes of the valid+ values below. The order of the cells should be++ - First Cell: CIU clock divider value (applicable only for Exynos5+ SoC's, should be zero for Exynos4 SoC's)+ - Second Cell: CIU clock phase shift value for tx mode.+ - Third Cell: CIU clock phase shift value for rx mode.++ Valid values for SDR and DDR CIU clock timing for Exynos5250:++ - valid values for CIU clock divider, tx phase shift and rx phase shift+ is 0 to 7.++ - When CIU clock divider value is set to 3, all possible 8 phase shift+ values can be used.++ - If CIU clock divider value is 0 (that is divide by 1), both tx and rx+ phase shift clocks should be 0.+ Example: The MSHC controller node can be split into two portions, SoC specific and board specific portions as listed below. dwmmc0 at 12200000 {- compatible = "snps,dw-mshc";+ compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; #address-cells = <1>;
@@ -2108,6 +2130,20 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)if(of_get_property(np,of_quriks[idx].quirk,NULL))pdata->quirks|=of_quriks[idx].id;+if(of_property_read_u32_array(dev->of_node,+"samsung,dw-mshc-sdr-timing",timing,3))+host->sdr_timing=DW_MCI_DEF_SDR_TIMING;+else+host->sdr_timing=SDMMC_CLKSEL_TIMING(timing[0],+timing[1],timing[2]);++if(of_property_read_u32_array(dev->of_node,+"samsung,dw-mshc-ddr-timing",timing,3))+host->ddr_timing=DW_MCI_DEF_DDR_TIMING;+else+host->ddr_timing=SDMMC_CLKSEL_TIMING(timing[0],+timing[1],timing[2]);+if(of_property_read_u32(np,"fifo-depth",&pdata->fifo_depth))dev_info(dev,"fifo-depth property not found, using ""value of FIFOTH register as default\n");
@@ -0,0 +1,108 @@+* Synopsis Designware Mobile Storage Host Controller++The Synopsis designware mobile storage host controller is used to interface+a SoC with storage medium such as eMMC or SD/MMC cards.++Required Properties:++* compatible: should be one of the following+ - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.++* reg: physical base address of the dw-mshc controller and size of its memory+ region.++* interrupts: interrupt specifier for the controller. The format and value of+ the interrupt specifier depends on the interrupt parent for the controller.++* #address-cells: should be 1.++* #size-cells: should be 0.++# Slots: The slot specific information are contained within child-nodes with+ each child-node representing a supported slot. There should be atleast one+ child node representing a card slot. The name of the child node representing+ the slot is recommended to be slot at n where n is the unique number of the slot+ connnected to the controller. The following are optional properties which+ can be included in the slot child node.++ * reg: specifies the physical slot number. The valid values of this+ property is 0 to (num-slots -1), where num-slots is the value+ specified by the num-slots property.++ * bus-width: specifies the width of the data bus connected from the+ controller to the card slot. The value should be 1, 4 or 8. In case+ this property is not specified, a default value of 1 is assumed for+ this property.++ * cd-gpios: specifies the card detect gpio line. The format of the+ gpio specifier depends on the gpio controller.++ * wp-gpios: specifies the write protect gpio line. The format of the+ gpio specifier depends on the gpio controller.++ * gpios: specifies a list of gpios used for command, clock and data+ bus. The first gpio is the command line and the second gpio is the+ clock line. The rest of the gpios (depending on the bus-width+ property) are the data lines in no particular order. The format of+ the gpio specifier depends on the gpio controller.++Optional properties:++* num-slots: specifies the number of slots supported by the controller.+ The number of physical slots actually used could be equal or less than the+ value specified by num-slots. If this property is not specified, the value+ of num-slot property is assumed to be 1.++* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not+ specified, the default value of the fifo size is determined from the+ controller registers.++* card-detect-delay: Delay in milli-seconds before detecting card after card+ insert event. The default value is 0.++* supports-highspeed: Enables support for high speed cards (upto 50MHz)++* card-detection-broken: The card detection functionality is not available on+ any of the slots.++* no-write-protect: The write protect pad of the controller is not connected+ to the write protect pin on the slot.++Aliases:++- All the MSHC controller nodes should be represented in the aliases node using+ the following format 'mshc{n}' where n is a unique number for the alias.+++Example:++ The MSHC controller node can be split into two portions, SoC specific and+ board specific portions as listed below.++ dwmmc0 at 12200000 {+ compatible = "snps,dw-mshc";+ reg = <0x12200000 0x1000>;+ interrupts = <0 75 0>;+ #address-cells = <1>;+ #size-cells = <0>;+ };++ dwmmc0 at 12200000 {+ num-slots = <1>;+ supports-highspeed;+ card-detection-broken;+ no-write-protect;+ fifo-depth = <0x80>;+ card-detect-delay = <200>;++ slot at 0 {+ reg = <0>;+ bus-width = <8>;+ cd-gpios = <&gpc0 2 2 3 3>;+ gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,+ <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,+ <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,+ <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,+ <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;+ };+ };
@@ -1762,10 +1768,106 @@ static void dw_mci_work_routine_card(struct work_struct *work)}}+#ifdef CONFIG_OF+staticstructdevice_node*dw_mci_of_find_slot_node(structdevice*dev,u8slot)+{+structdevice_node*np;+const__be32*addr;+intlen;++if(!dev||!dev->of_node)+returnNULL;++for_each_child_of_node(dev->of_node,np){+addr=of_get_property(np,"reg",&len);+if(!addr||(len<sizeof(int)))+continue;+if(be32_to_cpup(addr)==slot)+returnnp;+}+returnNULL;+}++staticu32dw_mci_of_get_bus_wd(structdevice*dev,u8slot)+{+structdevice_node*np=dw_mci_of_find_slot_node(dev,slot);+u32bus_wd=1;++if(!np)+return1;++if(of_property_read_u32(np,"bus-width",&bus_wd))+dev_err(dev,"bus-width property not found, assuming width"+" as 1\n");+returnbus_wd;+}++staticintdw_mci_of_setup_bus(structdw_mci*host,u8slot,u32bus_wd)+{+structdevice_node*np=dw_mci_of_find_slot_node(host->dev,slot);+intidx,gpio,ret;++if(!np)+return-EINVAL;++for(idx=0;idx<NUM_PINS(bus_wd);idx++){+gpio=of_get_gpio(np,idx);+if(!gpio_is_valid(gpio)){+dev_err(host->dev,"invalid gpio: %d\n",gpio);+return-EINVAL;+}++ret=devm_gpio_request(host->dev,gpio,"dw-mci-bus");+if(ret){+dev_err(host->dev,"gpio [%d] request failed\n",gpio);+return-EBUSY;+}+}++host->slot[slot]->wp_gpio=-1;+gpio=of_get_named_gpio(np,"wp-gpios",0);+if(!gpio_is_valid(gpio)){+dev_info(host->dev,"wp gpio not available");+}else{+ret=devm_gpio_request(host->dev,gpio,"dw-mci-wp");+if(ret)+dev_info(host->dev,"gpio [%d] request failed\n",+gpio);+else+host->slot[slot]->wp_gpio=gpio;+}++host->slot[slot]->cd_gpio=-1;+gpio=of_get_named_gpio(np,"cd-gpios",0);+if(!gpio_is_valid(gpio)){+dev_info(host->dev,"cd gpio not available");+}else{+ret=devm_gpio_request(host->dev,gpio,"dw-mci-cd");+if(ret)+dev_err(host->dev,"gpio [%d] request failed\n",gpio);+else+host->slot[slot]->cd_gpio=gpio;+}++return0;+}+#else /* CONFIG_OF */+staticu32dw_mci_of_get_bus_wd(structdevice*dev,u8slot)+{+return1;+}++staticintdw_mci_of_setup_bus(structdw_mci*host,u8slot,u32bus_wd)+{+return-EINVAL;+}+#endif /* CONFIG_OF */+staticint__initdw_mci_init_slot(structdw_mci*host,unsignedintid){structmmc_host*mmc;structdw_mci_slot*slot;+intctrl_id,ret;mmc=mmc_alloc_host(sizeof(structdw_mci_slot),host->dev);if(!mmc)
@@ -1775,6 +1877,7 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)slot->id=id;slot->mmc=mmc;slot->host=host;+host->slot[id]=slot;mmc->ops=&dw_mci_ops;mmc->f_min=DIV_ROUND_UP(host->bus_hz,510);
@@ -1795,12 +1898,33 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)if(host->pdata->caps)mmc->caps=host->pdata->caps;+if(host->dev->of_node){+ctrl_id=of_alias_get_id(host->dev->of_node,"mshc");+if(ctrl_id<0)+ctrl_id=0;+}+if(host->drv_data->caps)+mmc->caps|=host->drv_data->caps[ctrl_id];+if(host->pdata->caps2)mmc->caps2=host->pdata->caps2;-if(host->pdata->get_bus_wd)+if(host->pdata->get_bus_wd){if(host->pdata->get_bus_wd(slot->id)>=4)mmc->caps|=MMC_CAP_4_BIT_DATA;+}elseif(host->dev->of_node){+unsignedintbus_width;+bus_width=dw_mci_of_get_bus_wd(host->dev,slot->id);+switch(bus_width){+case8:+mmc->caps|=MMC_CAP_8_BIT_DATA;+case4:+mmc->caps|=MMC_CAP_4_BIT_DATA;+}+ret=dw_mci_of_setup_bus(host,slot->id,bus_width);+if(ret)+gotoerr_setup_bus;+}if(host->pdata->quirks&DW_MCI_QUIRK_HIGHSPEED)mmc->caps|=MMC_CAP_SD_HIGHSPEED|MMC_CAP_MMC_HIGHSPEED;
@@ -1845,7 +1969,6 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)elseclear_bit(DW_MMC_CARD_PRESENT,&slot->flags);-host->slot[id]=slot;mmc_add_host(mmc);#if defined(CONFIG_DEBUG_FS)
@@ -1862,6 +1985,10 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)queue_work(host->card_workqueue,&host->card_work);return0;++err_setup_bus:+mmc_free_host(mmc);+return-EINVAL;}staticvoiddw_mci_cleanup_slot(structdw_mci_slot*slot,unsignedintid)
@@ -1937,16 +2064,78 @@ static bool mci_wait_reset(struct device *dev, struct dw_mci *host)returnfalse;}+#ifdef CONFIG_OF+staticstructdw_mci_of_quirks{+char*quirk;+intid;+}of_quriks[]={+{+.quirk="supports-highspeed",+.id=DW_MCI_QUIRK_HIGHSPEED,+},{+.quirk="card-detection-broken",+.id=DW_MCI_QUIRK_BROKEN_CARD_DETECTION,+},{+.quirk="no-write-protect",+.id=DW_MCI_QUIRK_NO_WRITE_PROTECT,+}+};++staticstructdw_mci_board*dw_mci_parse_dt(structdw_mci*host)+{+structdw_mci_board*pdata;+structdevice*dev=host->dev;+structdevice_node*np=dev->of_node;+intidx,cnt;++pdata=devm_kzalloc(dev,sizeof(*pdata),GFP_KERNEL);+if(!pdata){+dev_err(dev,"could not allocate memory for pdata\n");+returnERR_PTR(-ENOMEM);+}++/* find out number of slots supported */+if(of_property_read_u32(dev->of_node,"num-slots",+&pdata->num_slots)){+dev_info(dev,"num-slots property not found, "+"assuming 1 slot is available\n");+pdata->num_slots=1;+}++/* get quirks */+cnt=sizeof(of_quriks)/sizeof(structdw_mci_of_quirks);+for(idx=0;idx<cnt;idx++)+if(of_get_property(np,of_quriks[idx].quirk,NULL))+pdata->quirks|=of_quriks[idx].id;++if(of_property_read_u32(np,"fifo-depth",&pdata->fifo_depth))+dev_info(dev,"fifo-depth property not found, using "+"value of FIFOTH register as default\n");++of_property_read_u32(np,"card-detect-delay",&pdata->detect_delay_ms);++returnpdata;+}++#else /* CONFIG_OF */+staticstructdw_mci_board*dw_mci_parse_dt(structdw_mci*host)+{+returnERR_PTR(-EINVAL);+}+#endif /* CONFIG_OF */+intdw_mci_probe(structdw_mci*host){intwidth,i,ret=0;u32fifo_size;intinit_slots=0;-if(!host->pdata||!host->pdata->init){-dev_err(host->dev,-"Platform data must supply init function\n");-return-ENODEV;+if(!host->pdata){+host->pdata=dw_mci_parse_dt(host);+if(IS_ERR(host->pdata)){+dev_err(host->dev,"platform data not available\n");+return-EINVAL;+}}if(!host->pdata->select_slot&&host->pdata->num_slots>1){
From: Thomas Abraham <hidden> Date: 2012-07-12 12:41:51
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan <redacted>
Signed-off-by: Thomas Abraham <redacted>
---
drivers/mmc/host/dw_mmc.c | 42 +++++++++++++++++++++++++++++++++++++++---
include/linux/mmc/dw_mmc.h | 4 ++++
2 files changed, 43 insertions(+), 3 deletions(-)
@@ -1953,18 +1953,38 @@ int dw_mci_probe(struct dw_mci *host)return-ENODEV;}-if(!host->pdata->bus_hz){+host->biu_clk=clk_get(host->dev,"biu");+if(IS_ERR(host->biu_clk))+dev_dbg(host->dev,"biu clock not available\n");+else+clk_prepare_enable(host->biu_clk);++host->ciu_clk=clk_get(host->dev,"ciu");+if(IS_ERR(host->ciu_clk))+dev_dbg(host->dev,"ciu clock not available\n");+else+clk_prepare_enable(host->ciu_clk);++if(IS_ERR(host->ciu_clk))+host->bus_hz=host->pdata->bus_hz;+else+host->bus_hz=clk_get_rate(host->ciu_clk);++if(!host->bus_hz){dev_err(host->dev,"Platform data must supply bus speed\n");-return-ENODEV;+ret=-ENODEV;+gotoerr_clk;}-host->bus_hz=host->pdata->bus_hz;host->quirks=host->pdata->quirks;spin_lock_init(&host->lock);INIT_LIST_HEAD(&host->queue);+host->dma_ops=host->pdata->dma_ops;+dw_mci_init_dma(host);+/**Getthehostdatawidth-thisassumesthatHCONhasbeensetwith*thecorrectvalues.
From: Thomas Abraham <hidden> Date: 2012-07-12 12:42:31
Instead of aborting the probe in case a slot initialization fails, allow
initialization of as many slots as possible. If there are atleast one
instance of slot that is successfully initialized, allow the driver probe
to succeed.
Signed-off-by: Thomas Abraham <redacted>
---
drivers/mmc/host/dw_mmc.c | 23 +++++++++++++----------
1 files changed, 13 insertions(+), 10 deletions(-)
@@ -1939,6 +1939,7 @@ int dw_mci_probe(struct dw_mci *host){intwidth,i,ret=0;u32fifo_size;+intinit_slots=0;if(!host->pdata||!host->pdata->init){dev_err(host->dev,
@@ -2047,10 +2048,18 @@ int dw_mci_probe(struct dw_mci *host)/* We need at least one slot to succeed */for(i=0;i<host->num_slots;i++){ret=dw_mci_init_slot(host,i);-if(ret){-ret=-ENODEV;-gotoerr_init_slot;-}+if(ret)+dev_dbg(host->dev,"slot %d init failed\n",i);+else+init_slots++;+}++if(init_slots){+dev_info(host->dev,"%d slots initialized\n",init_slots);+}else{+dev_dbg(host->dev,"attempted to initialize %d slots, "+"but failed on all\n",host->num_slots);+gotoerr_init_slot;}/*
@@ -2085,12 +2094,6 @@ int dw_mci_probe(struct dw_mci *host)return0;err_init_slot:-/* De-init any initialized slots */-while(i>0){-if(host->slot[i])-dw_mci_cleanup_slot(host->slot[i],i);-i--;-}free_irq(host->irq,host);err_workqueue:
From: Girish K S <hidden> Date: 2012-07-13 09:11:40
On 12 July 2012 18:24, Thomas Abraham [off-list ref] wrote:
quoted hunk
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan <redacted>
Signed-off-by: Thomas Abraham <redacted>
---
drivers/mmc/host/dw_mmc.c | 42 +++++++++++++++++++++++++++++++++++++++---
include/linux/mmc/dw_mmc.h | 4 ++++
2 files changed, 43 insertions(+), 3 deletions(-)
@@ -1953,18 +1953,38 @@ int dw_mci_probe(struct dw_mci *host)return-ENODEV;}-if(!host->pdata->bus_hz){+host->biu_clk=clk_get(host->dev,"biu");+if(IS_ERR(host->biu_clk))+dev_dbg(host->dev,"biu clock not available\n");+else+clk_prepare_enable(host->biu_clk);++host->ciu_clk=clk_get(host->dev,"ciu");+if(IS_ERR(host->ciu_clk))+dev_dbg(host->dev,"ciu clock not available\n");+else+clk_prepare_enable(host->ciu_clk);++if(IS_ERR(host->ciu_clk))+host->bus_hz=host->pdata->bus_hz;+else+host->bus_hz=clk_get_rate(host->ciu_clk);++if(!host->bus_hz){dev_err(host->dev,"Platform data must supply bus speed\n");-return-ENODEV;+ret=-ENODEV;+gotoerr_clk;}-host->bus_hz=host->pdata->bus_hz;host->quirks=host->pdata->quirks;spin_lock_init(&host->lock);INIT_LIST_HEAD(&host->queue);+host->dma_ops=host->pdata->dma_ops;+dw_mci_init_dma(host);
This initialization is already done.
quoted hunk
+
/*
* Get the host data width - this assumes that HCON has been set with
* the correct values.
1.6.6.rc2
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@@ -0,0 +1,108 @@+* Synopsis Designware Mobile Storage Host Controller++The Synopsis designware mobile storage host controller is used to interface+a SoC with storage medium such as eMMC or SD/MMC cards.++Required Properties:++* compatible: should be one of the following+ - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.++* reg: physical base address of the dw-mshc controller and size of its memory+ region.++* interrupts: interrupt specifier for the controller. The format and value of+ the interrupt specifier depends on the interrupt parent for the controller.++* #address-cells: should be 1.++* #size-cells: should be 0.++# Slots: The slot specific information are contained within child-nodes with+ each child-node representing a supported slot. There should be atleast one+ child node representing a card slot. The name of the child node representing+ the slot is recommended to be slot at n where n is the unique number of the slot+ connnected to the controller. The following are optional properties which+ can be included in the slot child node.++ * reg: specifies the physical slot number. The valid values of this+ property is 0 to (num-slots -1), where num-slots is the value+ specified by the num-slots property.++ * bus-width: specifies the width of the data bus connected from the+ controller to the card slot. The value should be 1, 4 or 8. In case+ this property is not specified, a default value of 1 is assumed for+ this property.++ * cd-gpios: specifies the card detect gpio line. The format of the+ gpio specifier depends on the gpio controller.++ * wp-gpios: specifies the write protect gpio line. The format of the+ gpio specifier depends on the gpio controller.++ * gpios: specifies a list of gpios used for command, clock and data+ bus. The first gpio is the command line and the second gpio is the+ clock line. The rest of the gpios (depending on the bus-width+ property) are the data lines in no particular order. The format of+ the gpio specifier depends on the gpio controller.++Optional properties:++* num-slots: specifies the number of slots supported by the controller.+ The number of physical slots actually used could be equal or less than the+ value specified by num-slots. If this property is not specified, the value+ of num-slot property is assumed to be 1.++* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not+ specified, the default value of the fifo size is determined from the+ controller registers.++* card-detect-delay: Delay in milli-seconds before detecting card after card+ insert event. The default value is 0.++* supports-highspeed: Enables support for high speed cards (upto 50MHz)++* card-detection-broken: The card detection functionality is not available on+ any of the slots.++* no-write-protect: The write protect pad of the controller is not connected+ to the write protect pin on the slot.++Aliases:++- All the MSHC controller nodes should be represented in the aliases node using+ the following format 'mshc{n}' where n is a unique number for the alias.+++Example:++ The MSHC controller node can be split into two portions, SoC specific and+ board specific portions as listed below.++ dwmmc0 at 12200000 {+ compatible = "snps,dw-mshc";+ reg = <0x12200000 0x1000>;+ interrupts = <0 75 0>;+ #address-cells = <1>;+ #size-cells = <0>;+ };++ dwmmc0 at 12200000 {+ num-slots = <1>;+ supports-highspeed;+ card-detection-broken;+ no-write-protect;+ fifo-depth = <0x80>;+ card-detect-delay = <200>;++ slot at 0 {+ reg = <0>;+ bus-width = <8>;+ cd-gpios = <&gpc0 2 2 3 3>;+ gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,+ <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,+ <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,+ <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,+ <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;+ };+ };
@@ -51,6 +67,13 @@ static int dw_mci_pltfm_probe(struct platform_device *pdev) if (!host->regs) goto err_free; platform_set_drvdata(pdev, host);++ if (pdev->dev.of_node) {+ const struct of_device_id *match;+ match = of_match_node(dw_mci_pltfm_match, pdev->dev.of_node);
can be modified to of_match_node(of_match_pt(dw_mci_pltfm_match),
pdev->dev.of_node);
This will remove the dummy allocation of variable as mentioned above.
Also it will be generic in non dt case.
quoted hunk
+ host->drv_data = match->data;
+ }
+
ret = dw_mci_probe(host);
if (ret)
goto err_out;
@@ -1762,10 +1768,106 @@ static void dw_mci_work_routine_card(struct work_struct *work)}}+#ifdef CONFIG_OF+staticstructdevice_node*dw_mci_of_find_slot_node(structdevice*dev,u8slot)+{+structdevice_node*np;+const__be32*addr;+intlen;++if(!dev||!dev->of_node)+returnNULL;++for_each_child_of_node(dev->of_node,np){+addr=of_get_property(np,"reg",&len);+if(!addr||(len<sizeof(int)))+continue;+if(be32_to_cpup(addr)==slot)+returnnp;+}+returnNULL;+}++staticu32dw_mci_of_get_bus_wd(structdevice*dev,u8slot)+{+structdevice_node*np=dw_mci_of_find_slot_node(dev,slot);+u32bus_wd=1;++if(!np)+return1;++if(of_property_read_u32(np,"bus-width",&bus_wd))+dev_err(dev,"bus-width property not found, assuming width"+" as 1\n");+returnbus_wd;+}++staticintdw_mci_of_setup_bus(structdw_mci*host,u8slot,u32bus_wd)+{+structdevice_node*np=dw_mci_of_find_slot_node(host->dev,slot);+intidx,gpio,ret;++if(!np)+return-EINVAL;++for(idx=0;idx<NUM_PINS(bus_wd);idx++){+gpio=of_get_gpio(np,idx);+if(!gpio_is_valid(gpio)){+dev_err(host->dev,"invalid gpio: %d\n",gpio);+return-EINVAL;+}++ret=devm_gpio_request(host->dev,gpio,"dw-mci-bus");+if(ret){+dev_err(host->dev,"gpio [%d] request failed\n",gpio);+return-EBUSY;+}+}++host->slot[slot]->wp_gpio=-1;+gpio=of_get_named_gpio(np,"wp-gpios",0);+if(!gpio_is_valid(gpio)){+dev_info(host->dev,"wp gpio not available");+}else{+ret=devm_gpio_request(host->dev,gpio,"dw-mci-wp");+if(ret)+dev_info(host->dev,"gpio [%d] request failed\n",+gpio);+else+host->slot[slot]->wp_gpio=gpio;+}++host->slot[slot]->cd_gpio=-1;+gpio=of_get_named_gpio(np,"cd-gpios",0);+if(!gpio_is_valid(gpio)){+dev_info(host->dev,"cd gpio not available");+}else{+ret=devm_gpio_request(host->dev,gpio,"dw-mci-cd");+if(ret)+dev_err(host->dev,"gpio [%d] request failed\n",gpio);+else+host->slot[slot]->cd_gpio=gpio;+}++return0;+}+#else /* CONFIG_OF */+staticu32dw_mci_of_get_bus_wd(structdevice*dev,u8slot)+{+return1;+}++staticintdw_mci_of_setup_bus(structdw_mci*host,u8slot,u32bus_wd)+{+return-EINVAL;+}+#endif /* CONFIG_OF */+staticint__initdw_mci_init_slot(structdw_mci*host,unsignedintid){structmmc_host*mmc;structdw_mci_slot*slot;+intctrl_id,ret;mmc=mmc_alloc_host(sizeof(structdw_mci_slot),host->dev);if(!mmc)
@@ -1775,6 +1877,7 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)slot->id=id;slot->mmc=mmc;slot->host=host;+host->slot[id]=slot;mmc->ops=&dw_mci_ops;mmc->f_min=DIV_ROUND_UP(host->bus_hz,510);
@@ -1795,12 +1898,33 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)if(host->pdata->caps)mmc->caps=host->pdata->caps;+if(host->dev->of_node){+ctrl_id=of_alias_get_id(host->dev->of_node,"mshc");+if(ctrl_id<0)+ctrl_id=0;+}+if(host->drv_data->caps)+mmc->caps|=host->drv_data->caps[ctrl_id];+if(host->pdata->caps2)mmc->caps2=host->pdata->caps2;-if(host->pdata->get_bus_wd)+if(host->pdata->get_bus_wd){if(host->pdata->get_bus_wd(slot->id)>=4)mmc->caps|=MMC_CAP_4_BIT_DATA;+}elseif(host->dev->of_node){+unsignedintbus_width;+bus_width=dw_mci_of_get_bus_wd(host->dev,slot->id);+switch(bus_width){+case8:+mmc->caps|=MMC_CAP_8_BIT_DATA;+case4:+mmc->caps|=MMC_CAP_4_BIT_DATA;+}+ret=dw_mci_of_setup_bus(host,slot->id,bus_width);+if(ret)+gotoerr_setup_bus;+}if(host->pdata->quirks&DW_MCI_QUIRK_HIGHSPEED)mmc->caps|=MMC_CAP_SD_HIGHSPEED|MMC_CAP_MMC_HIGHSPEED;
@@ -1845,7 +1969,6 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)elseclear_bit(DW_MMC_CARD_PRESENT,&slot->flags);-host->slot[id]=slot;mmc_add_host(mmc);#if defined(CONFIG_DEBUG_FS)
@@ -1862,6 +1985,10 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)queue_work(host->card_workqueue,&host->card_work);return0;++err_setup_bus:+mmc_free_host(mmc);+return-EINVAL;}staticvoiddw_mci_cleanup_slot(structdw_mci_slot*slot,unsignedintid)
@@ -1937,16 +2064,78 @@ static bool mci_wait_reset(struct device *dev, struct dw_mci *host)returnfalse;}+#ifdef CONFIG_OF+staticstructdw_mci_of_quirks{+char*quirk;+intid;+}of_quriks[]={+{+.quirk="supports-highspeed",+.id=DW_MCI_QUIRK_HIGHSPEED,+},{+.quirk="card-detection-broken",+.id=DW_MCI_QUIRK_BROKEN_CARD_DETECTION,+},{+.quirk="no-write-protect",+.id=DW_MCI_QUIRK_NO_WRITE_PROTECT,+}+};++staticstructdw_mci_board*dw_mci_parse_dt(structdw_mci*host)+{+structdw_mci_board*pdata;+structdevice*dev=host->dev;+structdevice_node*np=dev->of_node;+intidx,cnt;++pdata=devm_kzalloc(dev,sizeof(*pdata),GFP_KERNEL);+if(!pdata){+dev_err(dev,"could not allocate memory for pdata\n");+returnERR_PTR(-ENOMEM);+}++/* find out number of slots supported */+if(of_property_read_u32(dev->of_node,"num-slots",+&pdata->num_slots)){+dev_info(dev,"num-slots property not found, "+"assuming 1 slot is available\n");+pdata->num_slots=1;+}++/* get quirks */+cnt=sizeof(of_quriks)/sizeof(structdw_mci_of_quirks);+for(idx=0;idx<cnt;idx++)+if(of_get_property(np,of_quriks[idx].quirk,NULL))+pdata->quirks|=of_quriks[idx].id;++if(of_property_read_u32(np,"fifo-depth",&pdata->fifo_depth))+dev_info(dev,"fifo-depth property not found, using "+"value of FIFOTH register as default\n");++of_property_read_u32(np,"card-detect-delay",&pdata->detect_delay_ms);++returnpdata;+}++#else /* CONFIG_OF */+staticstructdw_mci_board*dw_mci_parse_dt(structdw_mci*host)+{+returnERR_PTR(-EINVAL);+}+#endif /* CONFIG_OF */+intdw_mci_probe(structdw_mci*host){intwidth,i,ret=0;u32fifo_size;intinit_slots=0;-if(!host->pdata||!host->pdata->init){-dev_err(host->dev,-"Platform data must supply init function\n");-return-ENODEV;+if(!host->pdata){+host->pdata=dw_mci_parse_dt(host);+if(IS_ERR(host->pdata)){+dev_err(host->dev,"platform data not available\n");+return-EINVAL;+}}if(!host->pdata->select_slot&&host->pdata->num_slots>1){
1.6.6.rc2
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@@ -0,0 +1,108 @@+* Synopsis Designware Mobile Storage Host Controller++The Synopsis designware mobile storage host controller is used to interface+a SoC with storage medium such as eMMC or SD/MMC cards.++Required Properties:++* compatible: should be one of the following+ - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.++* reg: physical base address of the dw-mshc controller and size of its memory+ region.++* interrupts: interrupt specifier for the controller. The format and value of+ the interrupt specifier depends on the interrupt parent for the controller.++* #address-cells: should be 1.++* #size-cells: should be 0.++# Slots: The slot specific information are contained within child-nodes with+ each child-node representing a supported slot. There should be atleast one+ child node representing a card slot. The name of the child node representing+ the slot is recommended to be slot at n where n is the unique number of the slot+ connnected to the controller. The following are optional properties which+ can be included in the slot child node.++ * reg: specifies the physical slot number. The valid values of this+ property is 0 to (num-slots -1), where num-slots is the value+ specified by the num-slots property.++ * bus-width: specifies the width of the data bus connected from the+ controller to the card slot. The value should be 1, 4 or 8. In case+ this property is not specified, a default value of 1 is assumed for+ this property.++ * cd-gpios: specifies the card detect gpio line. The format of the+ gpio specifier depends on the gpio controller.++ * wp-gpios: specifies the write protect gpio line. The format of the+ gpio specifier depends on the gpio controller.++ * gpios: specifies a list of gpios used for command, clock and data+ bus. The first gpio is the command line and the second gpio is the+ clock line. The rest of the gpios (depending on the bus-width+ property) are the data lines in no particular order. The format of+ the gpio specifier depends on the gpio controller.++Optional properties:++* num-slots: specifies the number of slots supported by the controller.+ The number of physical slots actually used could be equal or less than the+ value specified by num-slots. If this property is not specified, the value+ of num-slot property is assumed to be 1.++* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not+ specified, the default value of the fifo size is determined from the+ controller registers.++* card-detect-delay: Delay in milli-seconds before detecting card after card+ insert event. The default value is 0.++* supports-highspeed: Enables support for high speed cards (upto 50MHz)++* card-detection-broken: The card detection functionality is not available on+ any of the slots.++* no-write-protect: The write protect pad of the controller is not connected+ to the write protect pin on the slot.++Aliases:++- All the MSHC controller nodes should be represented in the aliases node using+ the following format 'mshc{n}' where n is a unique number for the alias.+++Example:++ The MSHC controller node can be split into two portions, SoC specific and+ board specific portions as listed below.++ dwmmc0 at 12200000 {+ compatible = "snps,dw-mshc";+ reg = <0x12200000 0x1000>;+ interrupts = <0 75 0>;+ #address-cells = <1>;+ #size-cells = <0>;+ };++ dwmmc0 at 12200000 {+ num-slots = <1>;+ supports-highspeed;+ card-detection-broken;+ no-write-protect;+ fifo-depth = <0x80>;+ card-detect-delay = <200>;++ slot at 0 {+ reg = <0>;+ bus-width = <8>;+ cd-gpios = <&gpc0 2 2 3 3>;+ gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,+ <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,+ <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,+ <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,+ <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;+ };+ };
@@ -51,6 +67,13 @@ static int dw_mci_pltfm_probe(struct platform_device *pdev) if (!host->regs) goto err_free; platform_set_drvdata(pdev, host);++ if (pdev->dev.of_node) {+ const struct of_device_id *match;+ match = of_match_node(dw_mci_pltfm_match, pdev->dev.of_node);
can be modified to of_match_node(of_match_pt(dw_mci_pltfm_match),
pdev->dev.of_node);
This will remove the dummy allocation of variable as mentioned above.
Sorry not allocation but declaration
Also it will be generic in non dt case.
quoted
+ host->drv_data = match->data;
+ }
+
ret = dw_mci_probe(host);
if (ret)
goto err_out;
@@ -1762,10 +1768,106 @@ static void dw_mci_work_routine_card(struct work_struct *work)}}+#ifdef CONFIG_OF+staticstructdevice_node*dw_mci_of_find_slot_node(structdevice*dev,u8slot)+{+structdevice_node*np;+const__be32*addr;+intlen;++if(!dev||!dev->of_node)+returnNULL;++for_each_child_of_node(dev->of_node,np){+addr=of_get_property(np,"reg",&len);+if(!addr||(len<sizeof(int)))+continue;+if(be32_to_cpup(addr)==slot)+returnnp;+}+returnNULL;+}++staticu32dw_mci_of_get_bus_wd(structdevice*dev,u8slot)+{+structdevice_node*np=dw_mci_of_find_slot_node(dev,slot);+u32bus_wd=1;++if(!np)+return1;++if(of_property_read_u32(np,"bus-width",&bus_wd))+dev_err(dev,"bus-width property not found, assuming width"+" as 1\n");+returnbus_wd;+}++staticintdw_mci_of_setup_bus(structdw_mci*host,u8slot,u32bus_wd)+{+structdevice_node*np=dw_mci_of_find_slot_node(host->dev,slot);+intidx,gpio,ret;++if(!np)+return-EINVAL;++for(idx=0;idx<NUM_PINS(bus_wd);idx++){+gpio=of_get_gpio(np,idx);+if(!gpio_is_valid(gpio)){+dev_err(host->dev,"invalid gpio: %d\n",gpio);+return-EINVAL;+}++ret=devm_gpio_request(host->dev,gpio,"dw-mci-bus");+if(ret){+dev_err(host->dev,"gpio [%d] request failed\n",gpio);+return-EBUSY;+}+}++host->slot[slot]->wp_gpio=-1;+gpio=of_get_named_gpio(np,"wp-gpios",0);+if(!gpio_is_valid(gpio)){+dev_info(host->dev,"wp gpio not available");+}else{+ret=devm_gpio_request(host->dev,gpio,"dw-mci-wp");+if(ret)+dev_info(host->dev,"gpio [%d] request failed\n",+gpio);+else+host->slot[slot]->wp_gpio=gpio;+}++host->slot[slot]->cd_gpio=-1;+gpio=of_get_named_gpio(np,"cd-gpios",0);+if(!gpio_is_valid(gpio)){+dev_info(host->dev,"cd gpio not available");+}else{+ret=devm_gpio_request(host->dev,gpio,"dw-mci-cd");+if(ret)+dev_err(host->dev,"gpio [%d] request failed\n",gpio);+else+host->slot[slot]->cd_gpio=gpio;+}++return0;+}+#else /* CONFIG_OF */+staticu32dw_mci_of_get_bus_wd(structdevice*dev,u8slot)+{+return1;+}++staticintdw_mci_of_setup_bus(structdw_mci*host,u8slot,u32bus_wd)+{+return-EINVAL;+}+#endif /* CONFIG_OF */+staticint__initdw_mci_init_slot(structdw_mci*host,unsignedintid){structmmc_host*mmc;structdw_mci_slot*slot;+intctrl_id,ret;mmc=mmc_alloc_host(sizeof(structdw_mci_slot),host->dev);if(!mmc)
@@ -1775,6 +1877,7 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)slot->id=id;slot->mmc=mmc;slot->host=host;+host->slot[id]=slot;mmc->ops=&dw_mci_ops;mmc->f_min=DIV_ROUND_UP(host->bus_hz,510);
@@ -1795,12 +1898,33 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)if(host->pdata->caps)mmc->caps=host->pdata->caps;+if(host->dev->of_node){+ctrl_id=of_alias_get_id(host->dev->of_node,"mshc");+if(ctrl_id<0)+ctrl_id=0;+}+if(host->drv_data->caps)+mmc->caps|=host->drv_data->caps[ctrl_id];+if(host->pdata->caps2)mmc->caps2=host->pdata->caps2;-if(host->pdata->get_bus_wd)+if(host->pdata->get_bus_wd){if(host->pdata->get_bus_wd(slot->id)>=4)mmc->caps|=MMC_CAP_4_BIT_DATA;+}elseif(host->dev->of_node){+unsignedintbus_width;+bus_width=dw_mci_of_get_bus_wd(host->dev,slot->id);+switch(bus_width){+case8:+mmc->caps|=MMC_CAP_8_BIT_DATA;+case4:+mmc->caps|=MMC_CAP_4_BIT_DATA;+}+ret=dw_mci_of_setup_bus(host,slot->id,bus_width);+if(ret)+gotoerr_setup_bus;+}if(host->pdata->quirks&DW_MCI_QUIRK_HIGHSPEED)mmc->caps|=MMC_CAP_SD_HIGHSPEED|MMC_CAP_MMC_HIGHSPEED;
@@ -1845,7 +1969,6 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)elseclear_bit(DW_MMC_CARD_PRESENT,&slot->flags);-host->slot[id]=slot;mmc_add_host(mmc);#if defined(CONFIG_DEBUG_FS)
@@ -1862,6 +1985,10 @@ static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)queue_work(host->card_workqueue,&host->card_work);return0;++err_setup_bus:+mmc_free_host(mmc);+return-EINVAL;}staticvoiddw_mci_cleanup_slot(structdw_mci_slot*slot,unsignedintid)
@@ -1937,16 +2064,78 @@ static bool mci_wait_reset(struct device *dev, struct dw_mci *host)returnfalse;}+#ifdef CONFIG_OF+staticstructdw_mci_of_quirks{+char*quirk;+intid;+}of_quriks[]={+{+.quirk="supports-highspeed",+.id=DW_MCI_QUIRK_HIGHSPEED,+},{+.quirk="card-detection-broken",+.id=DW_MCI_QUIRK_BROKEN_CARD_DETECTION,+},{+.quirk="no-write-protect",+.id=DW_MCI_QUIRK_NO_WRITE_PROTECT,+}+};++staticstructdw_mci_board*dw_mci_parse_dt(structdw_mci*host)+{+structdw_mci_board*pdata;+structdevice*dev=host->dev;+structdevice_node*np=dev->of_node;+intidx,cnt;++pdata=devm_kzalloc(dev,sizeof(*pdata),GFP_KERNEL);+if(!pdata){+dev_err(dev,"could not allocate memory for pdata\n");+returnERR_PTR(-ENOMEM);+}++/* find out number of slots supported */+if(of_property_read_u32(dev->of_node,"num-slots",+&pdata->num_slots)){+dev_info(dev,"num-slots property not found, "+"assuming 1 slot is available\n");+pdata->num_slots=1;+}++/* get quirks */+cnt=sizeof(of_quriks)/sizeof(structdw_mci_of_quirks);+for(idx=0;idx<cnt;idx++)+if(of_get_property(np,of_quriks[idx].quirk,NULL))+pdata->quirks|=of_quriks[idx].id;++if(of_property_read_u32(np,"fifo-depth",&pdata->fifo_depth))+dev_info(dev,"fifo-depth property not found, using "+"value of FIFOTH register as default\n");++of_property_read_u32(np,"card-detect-delay",&pdata->detect_delay_ms);++returnpdata;+}++#else /* CONFIG_OF */+staticstructdw_mci_board*dw_mci_parse_dt(structdw_mci*host)+{+returnERR_PTR(-EINVAL);+}+#endif /* CONFIG_OF */+intdw_mci_probe(structdw_mci*host){intwidth,i,ret=0;u32fifo_size;intinit_slots=0;-if(!host->pdata||!host->pdata->init){-dev_err(host->dev,-"Platform data must supply init function\n");-return-ENODEV;+if(!host->pdata){+host->pdata=dw_mci_parse_dt(host);+if(IS_ERR(host->pdata)){+dev_err(host->dev,"platform data not available\n");+return-EINVAL;+}}if(!host->pdata->select_slot&&host->pdata->num_slots>1){
1.6.6.rc2
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@@ -51,6 +67,13 @@ static int dw_mci_pltfm_probe(struct platform_device *pdev) if (!host->regs) goto err_free; platform_set_drvdata(pdev, host);++ if (pdev->dev.of_node) {+ const struct of_device_id *match;+ match = of_match_node(dw_mci_pltfm_match, pdev->dev.of_node);
can be modified to of_match_node(of_match_pt(dw_mci_pltfm_match),
pdev->dev.of_node);
This will remove the dummy allocation of variable as mentioned above.
Also it will be generic in non dt case.
Ok. Thanks for the suggestion. I will modify it as per your suggestion.
Thanks,
Thomas.
[...]
From: Thomas Abraham <hidden> Date: 2012-07-17 10:24:42
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan <redacted>
Signed-off-by: Thomas Abraham <redacted>
---
drivers/mmc/host/dw_mmc.c | 39 ++++++++++++++++++++++++++++++++++++---
include/linux/mmc/dw_mmc.h | 4 ++++
2 files changed, 40 insertions(+), 3 deletions(-)
@@ -1953,13 +1953,30 @@ int dw_mci_probe(struct dw_mci *host)return-ENODEV;}-if(!host->pdata->bus_hz){+host->biu_clk=clk_get(host->dev,"biu");+if(IS_ERR(host->biu_clk))+dev_dbg(host->dev,"biu clock not available\n");+else+clk_prepare_enable(host->biu_clk);++host->ciu_clk=clk_get(host->dev,"ciu");+if(IS_ERR(host->ciu_clk))+dev_dbg(host->dev,"ciu clock not available\n");+else+clk_prepare_enable(host->ciu_clk);++if(IS_ERR(host->ciu_clk))+host->bus_hz=host->pdata->bus_hz;+else+host->bus_hz=clk_get_rate(host->ciu_clk);++if(!host->bus_hz){dev_err(host->dev,"Platform data must supply bus speed\n");-return-ENODEV;+ret=-ENODEV;+gotoerr_clk;}-host->bus_hz=host->pdata->bus_hz;host->quirks=host->pdata->quirks;spin_lock_init(&host->lock);
Hi,
This version does not seems to consider previous reviews fully.
Could you check the comments below?
July 12, 2012, Thomas Abraham [off-list ref] wrote:
quoted hunk
The instantiation of the Synopsis Designware controller on Exynos5250
include extension for SDR and DDR specific tx/rx phase shift timing
and CIU internal divider. In addition to that, the option to skip the
command hold stage is also introduced. Add support for these Exynos5250
specfic extenstions.
Signed-off-by: Abhilash Kesavan <redacted>
Signed-off-by: Thomas Abraham <redacted>
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 38 ++++++++++++++++++-
drivers/mmc/host/dw_mmc-pltfm.c | 15 +++++++
drivers/mmc/host/dw_mmc.c | 40 +++++++++++++++++++-
drivers/mmc/host/dw_mmc.h | 14 +++++++
include/linux/mmc/dw_mmc.h | 6 +++
5 files changed, 110 insertions(+), 3 deletions(-)
@@ -7,6 +7,8 @@ Required Properties: * compatible: should be one of the following - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.+ - samsung,exynos5250-dw-mshc: for controllers with Samsung+ Exynos5250 specific extentions. * reg: physical base address of the dw-mshc controller and size of its memory region.
@@ -74,13 +76,45 @@ Aliases: the following format 'mshc{n}' where n is a unique number for the alias.+Samsung Exynos4/5 specific properties:++Some of the variants of Exynos4 (such as Exynos4412) and Exynos5 SoC's+includes few extensions to the Synopsis Designware Mobile Storage Host+Controller. The following properties are used to describe those extensions.++* samsung,dw-mshc-sdr-timing: Specifies the value of CUI clock divider, CIU+ clock phase shift value in transmit mode and CIU clock phase shift value in+ receive mode for single data rate mode operation. Refer notes of the valid+ values below.++* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock divider, CIU+ clock phase shift value in transmit mode and CIU clock phase shift value in+ receive mode for double data rate mode operation. Refer notes of the valid+ values below. The order of the cells should be++ - First Cell: CIU clock divider value (applicable only for Exynos5+ SoC's, should be zero for Exynos4 SoC's)+ - Second Cell: CIU clock phase shift value for tx mode.+ - Third Cell: CIU clock phase shift value for rx mode.++ Valid values for SDR and DDR CIU clock timing for Exynos5250:++ - valid values for CIU clock divider, tx phase shift and rx phase shift+ is 0 to 7.++ - When CIU clock divider value is set to 3, all possible 8 phase shift+ values can be used.++ - If CIU clock divider value is 0 (that is divide by 1), both tx and rx+ phase shift clocks should be 0.+ Example: The MSHC controller node can be split into two portions, SoC specific and board specific portions as listed below. dwmmc0 at 12200000 {- compatible = "snps,dw-mshc";+ compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; #address-cells = <1>;
Kyungmin Park has already pointed .
It's not still proper place for board specific caps.
If I'm incorrect, please let me know.
And why MMC_CAP_CMD23 is default caps for all channel of hosts?
As you know, CLKSEL is specific for Samsung soc.
0x09C(CLKSEL) is reserved area in Synopsys memory map.
In case of non-samsung-soc, we cannot ensure this usage.
In previous version, I have suggested separating the variant into another file.
Is this patch considered only for exynos5250?
In case of exynos4210, the number of bits is different.
If upper macros is backward-compatible, it would be better.
Best regards,
Seungwon Jeon
@@ -166,6 +168,10 @@ struct dw_mci {structclk*ciu_clk;structdw_mci_slot*slot[MAX_MCI_SLOTS];+/* Phase Shift Value (for exynos5250 variant) */+u32sdr_timing;+u32ddr_timing;+/* FIFO push and pull */intfifo_depth;intdata_shift;--
1.6.6.rc2
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July 17, 2012, Thomas Abraham [off-list ref] wrote:
quoted hunk
Some platforms allow for clock gating and control of bus interface unit clock
and card interface unit clock. Add support for clock lookup of optional biu
and ciu clocks for clock gating and clock speed determination.
Signed-off-by: Abhilash Kesavan <redacted>
Signed-off-by: Thomas Abraham <redacted>
---
drivers/mmc/host/dw_mmc.c | 39 ++++++++++++++++++++++++++++++++++++---
include/linux/mmc/dw_mmc.h | 4 ++++
2 files changed, 40 insertions(+), 3 deletions(-)
@@ -1953,13 +1953,30 @@ int dw_mci_probe(struct dw_mci *host)return-ENODEV;}-if(!host->pdata->bus_hz){+host->biu_clk=clk_get(host->dev,"biu");+if(IS_ERR(host->biu_clk))+dev_dbg(host->dev,"biu clock not available\n");+else+clk_prepare_enable(host->biu_clk);++host->ciu_clk=clk_get(host->dev,"ciu");+if(IS_ERR(host->ciu_clk))+dev_dbg(host->dev,"ciu clock not available\n");+else+clk_prepare_enable(host->ciu_clk);++if(IS_ERR(host->ciu_clk))+host->bus_hz=host->pdata->bus_hz;+else+host->bus_hz=clk_get_rate(host->ciu_clk);
I have posted similar patch some time back.
bus_hz represents input rate for cclk_in of mshc.
Host of samsung soc doesn't use input clock from system directly.
As you have introduced CLKSEL in your another patch, input clock can be changed prior to cclk_in.
For non-samsung host, we don't need to consider this with generic way?
Thanks,
Seungwon Jeon
quoted hunk
+
+ if (!host->bus_hz) {
dev_err(host->dev,
"Platform data must supply bus speed\n");
- return -ENODEV;
+ ret = -ENODEV;
+ goto err_clk;
}
- host->bus_hz = host->pdata->bus_hz;
host->quirks = host->pdata->quirks;
spin_lock_init(&host->lock);
1.6.6.rc2
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Hi Thomas,
I think not good that added the samsung specific code into dw_mmc-pltfm.c
How about separating to dw-mmc-exynos.c?
Best Regards,
Jaehoon Chung
On 07/12/2012 09:54 PM, Thomas Abraham wrote:
This patch series adds device tree support for Synopsis Designware Mobile
Storage Host Controller.
The first patch converts the copy of controller device instance into a
reference. This is need to allow device resource management api to correctly
manage the resources allocated by the driver. The second patch fixes the
incorrect abort of the probe in case a slot initialization fails. This is
fixed by allowing as many slots to be initialized successfully and failing
only if there are no slots that were initialized.
The third patch adds clock lookup in the driver and this is optional. Platforms
that do not need any clock gating and control for the dw_mmc controllers will
not be affected with this change. The fourth patch adds a quirk to notify the
controller about the absence of the write protect line.
The fifth patch adds device tree based discovery support for the dw_mmc driver.
The sixth patch add Samsung Exynos5250 specific extentions to the driver.
This patchset is based on Samsung kernel tree's for-next branch with the
mmc tree's mmc-next branch merged.
Thomas Abraham (6):
mmc: dw_mmc: convert copy of struct device in struct dw_mci to a reference
mmc: dw_mmc: allow probe to succeed even if one slot is initialized
mmc: dw_mmc: lookup for optional biu and ciu clocks
mmc: dw_mmc: add quirk to indicate missing write protect line
mmc: dw_mmc: add device tree support
mmc: dw_mmc: add samsung exynos5250 specific extentions
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 144 ++++++++
drivers/mmc/host/dw_mmc-pci.c | 2 +-
drivers/mmc/host/dw_mmc-pltfm.c | 41 +++-
drivers/mmc/host/dw_mmc.c | 364 +++++++++++++++++---
drivers/mmc/host/dw_mmc.h | 23 ++
include/linux/mmc/dw_mmc.h | 17 +-
6 files changed, 538 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
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From: Thomas Abraham <hidden> Date: 2012-07-19 18:48:51
On 19 July 2012 09:21, Seungwon Jeon [off-list ref] wrote:
Hi,
This version does not seems to consider previous reviews fully.
Could you check the comments below?
I did try to address all the comments. I will check again and resubmit
if I have missed anything.
July 12, 2012, Thomas Abraham [off-list ref] wrote:
quoted
The instantiation of the Synopsis Designware controller on Exynos5250
include extension for SDR and DDR specific tx/rx phase shift timing
and CIU internal divider. In addition to that, the option to skip the
command hold stage is also introduced. Add support for these Exynos5250
specfic extenstions.
Signed-off-by: Abhilash Kesavan <redacted>
Signed-off-by: Thomas Abraham <redacted>
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 38 ++++++++++++++++++-
drivers/mmc/host/dw_mmc-pltfm.c | 15 +++++++
drivers/mmc/host/dw_mmc.c | 40 +++++++++++++++++++-
drivers/mmc/host/dw_mmc.h | 14 +++++++
include/linux/mmc/dw_mmc.h | 6 +++
5 files changed, 110 insertions(+), 3 deletions(-)
@@ -7,6 +7,8 @@ Required Properties: * compatible: should be one of the following - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.+ - samsung,exynos5250-dw-mshc: for controllers with Samsung+ Exynos5250 specific extentions. * reg: physical base address of the dw-mshc controller and size of its memory region.
@@ -74,13 +76,45 @@ Aliases: the following format 'mshc{n}' where n is a unique number for the alias.+Samsung Exynos4/5 specific properties:++Some of the variants of Exynos4 (such as Exynos4412) and Exynos5 SoC's+includes few extensions to the Synopsis Designware Mobile Storage Host+Controller. The following properties are used to describe those extensions.++* samsung,dw-mshc-sdr-timing: Specifies the value of CUI clock divider, CIU+ clock phase shift value in transmit mode and CIU clock phase shift value in+ receive mode for single data rate mode operation. Refer notes of the valid+ values below.++* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock divider, CIU+ clock phase shift value in transmit mode and CIU clock phase shift value in+ receive mode for double data rate mode operation. Refer notes of the valid+ values below. The order of the cells should be++ - First Cell: CIU clock divider value (applicable only for Exynos5+ SoC's, should be zero for Exynos4 SoC's)+ - Second Cell: CIU clock phase shift value for tx mode.+ - Third Cell: CIU clock phase shift value for rx mode.++ Valid values for SDR and DDR CIU clock timing for Exynos5250:++ - valid values for CIU clock divider, tx phase shift and rx phase shift+ is 0 to 7.++ - When CIU clock divider value is set to 3, all possible 8 phase shift+ values can be used.++ - If CIU clock divider value is 0 (that is divide by 1), both tx and rx+ phase shift clocks should be 0.+ Example: The MSHC controller node can be split into two portions, SoC specific and board specific portions as listed below. dwmmc0 at 12200000 {- compatible = "snps,dw-mshc";+ compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; #address-cells = <1>;
Kyungmin Park has already pointed .
It's not still proper place for board specific caps.
If I'm incorrect, please let me know.
And why MMC_CAP_CMD23 is default caps for all channel of hosts?
The cap listed above are specifying controller capabilities for dw-mmc
controllers on Exynos5 SoC. They are not board specific caps. All the
Exynos5 dw-mmc controllers can support MMC_CAP_CMD23 cap and hence, it
has been listed for all the controllers. Please let me know if you
feel there is any change required here.
As you know, CLKSEL is specific for Samsung soc.
0x09C(CLKSEL) is reserved area in Synopsys memory map.
In case of non-samsung-soc, we cannot ensure this usage.
In previous version, I have suggested separating the variant into another file.
There is a check for type of SoC before using 0x9C as CLKSEL register.
Other implementations of dw-mmc might define custom register at 0x9C
but this will code will not execute on other SoC's and will not break
anything on other implementations. Regarding spliting this Exynos
specific code into another file, I prefer not to do it for now.
Spliting the code means adding new definitions of callback functions
which I am not sure is really required. The present code is fairly
simple one.
Host of non-samsung will reach here.
host->sdr_timing is needed for this host? host->ddr_timing is the same.
Yes, but non-samsung hosts will not have have this property into their
dts file. So the code within the condition will not execute on
non-samsung hosts. SDR and DDR timing are required for Exynos5 SoC.
quoted
+ else
+ host->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
+ if (of_property_read_u32_array(dev->of_node,
+ "samsung,dw-mshc-ddr-timing", timing, 3))
+ host->ddr_timing = DW_MCI_DEF_DDR_TIMING;
+ else
+ host->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
dev_info(dev, "fifo-depth property not found, using "
"value of FIFOTH register as default\n");
Is this patch considered only for exynos5250?
In case of exynos4210, the number of bits is different.
If upper macros is backward-compatible, it would be better.
These consider the Exynos4210 and Exynos4412 implementations as well.
The device tree documentation clearly states that the possible values
for each of the dividers. For Exynos4 SoC's, the divider value is
between 1 to 4 (or 0 to 3). So a bit mask of 7 is backward compatilble
for Exynos4.
Thanks for your review and comments on this patch.
Regards,
Thomas.
@@ -166,6 +168,10 @@ struct dw_mci {structclk*ciu_clk;structdw_mci_slot*slot[MAX_MCI_SLOTS];+/* Phase Shift Value (for exynos5250 variant) */+u32sdr_timing;+u32ddr_timing;+/* FIFO push and pull */intfifo_depth;intdata_shift;--
1.6.6.rc2
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From: Thomas Abraham <hidden> Date: 2012-07-19 18:59:14
On 19 July 2012 20:58, Jaehoon Chung [off-list ref] wrote:
Hi Thomas,
I think not good that added the samsung specific code into dw_mmc-pltfm.c
How about separating to dw-mmc-exynos.c?
I am not sure of this. The only samsung specific code in
dw_mmc-pltfm.c file is the data for of_device_id instances. The clock
lookup added into this file in the 3rd patch does not cause any harm
on non-samsung SoC's which might not define those clocks (on clock
lookup failure, there are only warning printed, the driver's probe
does not fail.
I would prefer not to add separate file for Exynos SoC's for now.
Splitting into different files will need to defined new callbacks
which I fell is not really required.
Thanks,
Thomas.
Best Regards,
Jaehoon Chung
On 07/12/2012 09:54 PM, Thomas Abraham wrote:
quoted
This patch series adds device tree support for Synopsis Designware Mobile
Storage Host Controller.
The first patch converts the copy of controller device instance into a
reference. This is need to allow device resource management api to correctly
manage the resources allocated by the driver. The second patch fixes the
incorrect abort of the probe in case a slot initialization fails. This is
fixed by allowing as many slots to be initialized successfully and failing
only if there are no slots that were initialized.
The third patch adds clock lookup in the driver and this is optional. Platforms
that do not need any clock gating and control for the dw_mmc controllers will
not be affected with this change. The fourth patch adds a quirk to notify the
controller about the absence of the write protect line.
The fifth patch adds device tree based discovery support for the dw_mmc driver.
The sixth patch add Samsung Exynos5250 specific extentions to the driver.
This patchset is based on Samsung kernel tree's for-next branch with the
mmc tree's mmc-next branch merged.
Thomas Abraham (6):
mmc: dw_mmc: convert copy of struct device in struct dw_mci to a reference
mmc: dw_mmc: allow probe to succeed even if one slot is initialized
mmc: dw_mmc: lookup for optional biu and ciu clocks
mmc: dw_mmc: add quirk to indicate missing write protect line
mmc: dw_mmc: add device tree support
mmc: dw_mmc: add samsung exynos5250 specific extentions
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 144 ++++++++
drivers/mmc/host/dw_mmc-pci.c | 2 +-
drivers/mmc/host/dw_mmc-pltfm.c | 41 +++-
drivers/mmc/host/dw_mmc.c | 364 +++++++++++++++++---
drivers/mmc/host/dw_mmc.h | 23 ++
include/linux/mmc/dw_mmc.h | 17 +-
6 files changed, 538 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
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From: Kukjin Kim <hidden> Date: 2012-07-19 22:47:37
Thomas Abraham wrote:
On 19 July 2012 20:58, Jaehoon Chung [off-list ref] wrote:
quoted
Hi Thomas,
I think not good that added the samsung specific code into dw_mmc-
pltfm.c
quoted
How about separating to dw-mmc-exynos.c?
I am not sure of this. The only samsung specific code in
dw_mmc-pltfm.c file is the data for of_device_id instances. The clock
lookup added into this file in the 3rd patch does not cause any harm
on non-samsung SoC's which might not define those clocks (on clock
lookup failure, there are only warning printed, the driver's probe
does not fail.
I agree with Thomas' opinion, in addition, the dw_mmc-pltfm.c file can
support that, so adding dw-mmc-exynos.c is not needed now.
I would prefer not to add separate file for Exynos SoC's for now.
Splitting into different files will need to defined new callbacks
which I fell is not really required.
Yes.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim [off-list ref], Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
July 20, 2012, Thomas Abraham [off-list ref] wrote:
On 19 July 2012 09:21, Seungwon Jeon [off-list ref] wrote:
quoted
Hi,
This version does not seems to consider previous reviews fully.
Could you check the comments below?
I did try to address all the comments. I will check again and resubmit
if I have missed anything.
quoted
July 12, 2012, Thomas Abraham [off-list ref] wrote:
quoted
The instantiation of the Synopsis Designware controller on Exynos5250
include extension for SDR and DDR specific tx/rx phase shift timing
and CIU internal divider. In addition to that, the option to skip the
command hold stage is also introduced. Add support for these Exynos5250
specfic extenstions.
Signed-off-by: Abhilash Kesavan <redacted>
Signed-off-by: Thomas Abraham <redacted>
---
.../devicetree/bindings/mmc/synposis-dw-mshc.txt | 38 ++++++++++++++++++-
drivers/mmc/host/dw_mmc-pltfm.c | 15 +++++++
drivers/mmc/host/dw_mmc.c | 40 +++++++++++++++++++-
drivers/mmc/host/dw_mmc.h | 14 +++++++
include/linux/mmc/dw_mmc.h | 6 +++
5 files changed, 110 insertions(+), 3 deletions(-)
@@ -7,6 +7,8 @@ Required Properties: * compatible: should be one of the following - snps,dw-mshc: for controllers compliant with synopsis dw-mshc.+ - samsung,exynos5250-dw-mshc: for controllers with Samsung+ Exynos5250 specific extentions. * reg: physical base address of the dw-mshc controller and size of its memory region.
@@ -74,13 +76,45 @@ Aliases: the following format 'mshc{n}' where n is a unique number for the alias.+Samsung Exynos4/5 specific properties:++Some of the variants of Exynos4 (such as Exynos4412) and Exynos5 SoC's+includes few extensions to the Synopsis Designware Mobile Storage Host+Controller. The following properties are used to describe those extensions.++* samsung,dw-mshc-sdr-timing: Specifies the value of CUI clock divider, CIU+ clock phase shift value in transmit mode and CIU clock phase shift value in+ receive mode for single data rate mode operation. Refer notes of the valid+ values below.++* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock divider, CIU+ clock phase shift value in transmit mode and CIU clock phase shift value in+ receive mode for double data rate mode operation. Refer notes of the valid+ values below. The order of the cells should be++ - First Cell: CIU clock divider value (applicable only for Exynos5+ SoC's, should be zero for Exynos4 SoC's)+ - Second Cell: CIU clock phase shift value for tx mode.+ - Third Cell: CIU clock phase shift value for rx mode.++ Valid values for SDR and DDR CIU clock timing for Exynos5250:++ - valid values for CIU clock divider, tx phase shift and rx phase shift+ is 0 to 7.++ - When CIU clock divider value is set to 3, all possible 8 phase shift+ values can be used.++ - If CIU clock divider value is 0 (that is divide by 1), both tx and rx+ phase shift clocks should be 0.+ Example: The MSHC controller node can be split into two portions, SoC specific and board specific portions as listed below. dwmmc0 at 12200000 {- compatible = "snps,dw-mshc";+ compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; #address-cells = <1>;
Kyungmin Park has already pointed .
It's not still proper place for board specific caps.
If I'm incorrect, please let me know.
And why MMC_CAP_CMD23 is default caps for all channel of hosts?
The cap listed above are specifying controller capabilities for dw-mmc
controllers on Exynos5 SoC. They are not board specific caps. All the
Exynos5 dw-mmc controllers can support MMC_CAP_CMD23 cap and hence, it
has been listed for all the controllers. Please let me know if you
feel there is any change required here.
MMC_CAP_8_BIT_DATA could be dependent on board.
I agree about MMC_CAP_CMD23.
Additionally, MMC_CAP_CMD23 is applied for dw-mmc host driver without regard to Exynos5.
cmdr |= SDMMC_CMD_DAT_WR;
}
+ /*
+ * Samsung Exynos5250 extends the use of CMD register with the use of
+ * bit 29 (which is reserved on standard MSHC controllers) for
+ * optionally bypassing the HOLD register for command and data. The
+ * HOLD register should be bypassed in case there is no phase shift
+ * applied on CMD/DATA that is sent to the card.
+ */
+ if (slot->host->drv_data->ctrl_type == DW_MCI_TYPE_EXYNOS5250)
+ if (SDMMC_CLKSEL_GET_SELCLK_DRV(mci_readl(slot->host, CLKSEL)))
+ cmdr |= SDMMC_CMD_USE_HOLD_REG;
+
return cmdr;
}
As you know, CLKSEL is specific for Samsung soc.
0x09C(CLKSEL) is reserved area in Synopsys memory map.
In case of non-samsung-soc, we cannot ensure this usage.
In previous version, I have suggested separating the variant into another file.
There is a check for type of SoC before using 0x9C as CLKSEL register.
Do you mean checking DW_MCI_TYPE_EXYNOS5250?
But Above two case(ddr_timing/sdr_timing), CLKSEL can be accessed on other soc's.
Other implementations of dw-mmc might define custom register at 0x9C
Even so, register field can be different with Samsung soc.
but this will code will not execute on other SoC's and will not break
anything on other implementations. Regarding spliting this Exynos
specific code into another file, I prefer not to do it for now.
Spliting the code means adding new definitions of callback functions
which I am not sure is really required. The present code is fairly
simple one.
Yes, callback functions might be needed to accommodate various implementation
of host controller. It would be better to prepare this for other variant next.
Host of non-samsung will reach here.
host->sdr_timing is needed for this host? host->ddr_timing is the same.
Yes, but non-samsung hosts will not have have this property into their
dts file. So the code within the condition will not execute on
non-samsung hosts. SDR and DDR timing are required for Exynos5 SoC.
Yes, these are required only for Exynos Soc.
Non-samsung host will have default value here, but it seems to be meaningless.
quoted
quoted
+ else
+ host->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
+ if (of_property_read_u32_array(dev->of_node,
+ "samsung,dw-mshc-ddr-timing", timing, 3))
+ host->ddr_timing = DW_MCI_DEF_DDR_TIMING;
+ else
+ host->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
dev_info(dev, "fifo-depth property not found, using "
"value of FIFOTH register as default\n");
Is this patch considered only for exynos5250?
In case of exynos4210, the number of bits is different.
If upper macros is backward-compatible, it would be better.
These consider the Exynos4210 and Exynos4412 implementations as well.
The device tree documentation clearly states that the possible values
for each of the dividers. For Exynos4 SoC's, the divider value is
between 1 to 4 (or 0 to 3). So a bit mask of 7 is backward compatilble
for Exynos4.
Bit width is 2 for selclk_drv in exynos4210.
So bit mask of 3 is proper.
Let me clear it about divider value.
In case of Exynos4 SoC's, divider value(DIVRATIO) is reserved and host doesn't modify.
But value is fixed internally like following.
Exynos4210 : 2
Exynos4412 : 4
Thanks,
Seungwon Jeon
Thanks for your review and comments on this patch.
Regards,
Thomas.
@@ -166,6 +168,10 @@ struct dw_mci {structclk*ciu_clk;structdw_mci_slot*slot[MAX_MCI_SLOTS];+/* Phase Shift Value (for exynos5250 variant) */+u32sdr_timing;+u32ddr_timing;+/* FIFO push and pull */intfifo_depth;intdata_shift;--
1.6.6.rc2
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On 19 July 2012 20:58, Jaehoon Chung [off-list ref] wrote:
quoted
Hi Thomas,
I think not good that added the samsung specific code into dw_mmc-
pltfm.c
quoted
How about separating to dw-mmc-exynos.c?
I am not sure of this. The only samsung specific code in
dw_mmc-pltfm.c file is the data for of_device_id instances. The clock
lookup added into this file in the 3rd patch does not cause any harm
on non-samsung SoC's which might not define those clocks (on clock
lookup failure, there are only warning printed, the driver's probe
does not fail.
I agree with Thomas' opinion, in addition, the dw_mmc-pltfm.c file can
support that, so adding dw-mmc-exynos.c is not needed now.
quoted
I would prefer not to add separate file for Exynos SoC's for now.
Splitting into different files will need to defined new callbacks
which I fell is not really required.
Then where is the callback function located?
Best Regards,
Jaehoon Chung
quoted
Yes.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim [off-list ref], Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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Kyungmin Park has already pointed .
It's not still proper place for board specific caps.
If I'm incorrect, please let me know.
And why MMC_CAP_CMD23 is default caps for all channel of hosts?
The cap listed above are specifying controller capabilities for dw-mmc
controllers on Exynos5 SoC. They are not board specific caps. All the
Exynos5 dw-mmc controllers can support MMC_CAP_CMD23 cap and hence, it
has been listed for all the controllers. Please let me know if you
feel there is any change required here.
MMC_CAP_8_BIT_DATA could be dependent on board.
A controller can have the MMC_CAP_8_BIT_DATA capability but the board
will decide the bus-width. The bus-width is specified in the dts files
of each board (or platform data). The bus-width for data transfer is
then decided by the MMC core code based on the caps and the bus-width
information. So MMC_CAP_8_BIT_DATA can be specified irrespective of
whether the board supports 8-bit or not.
I agree about MMC_CAP_CMD23.
Additionally, MMC_CAP_CMD23 is applied for dw-mmc host driver without regard to Exynos5.
The caps listed in exynos5250_dwmmc_caps is applicable only for
Exynos5 SoC's. Could you please let me know if there is anything
incorrect here.
[...]
As you know, CLKSEL is specific for Samsung soc.
0x09C(CLKSEL) is reserved area in Synopsys memory map.
In case of non-samsung-soc, we cannot ensure this usage.
In previous version, I have suggested separating the variant into another file.
There is a check for type of SoC before using 0x9C as CLKSEL register.
Do you mean checking DW_MCI_TYPE_EXYNOS5250?
But Above two case(ddr_timing/sdr_timing), CLKSEL can be accessed on other soc's.
The tests have only been completed on Exynos5250. I do not have boards
for other Samsung SoC's which have a dw_mmc port connected and used on
the board. When we have other platforms tested with this patchset, we
can extend the 'if' check in the above code for other SoC's.
quoted
Other implementations of dw-mmc might define custom register at 0x9C
Even so, register field can be different with Samsung soc.
Yes, with the correct checks for the type of SoC, differences in the
usage of 0x9C register can be handled.
quoted
but this will code will not execute on other SoC's and will not break
anything on other implementations. Regarding spliting this Exynos
specific code into another file, I prefer not to do it for now.
Spliting the code means adding new definitions of callback functions
which I am not sure is really required. The present code is fairly
simple one.
Yes, callback functions might be needed to accommodate various implementation
of host controller. It would be better to prepare this for other variant next.
Ok. I will relook at these patches and check if we really need split
these changes into a separate exynos specific file. If I again feel
that such a split is not required, I will reply back to you with
justification.
[...]
Host of non-samsung will reach here.
host->sdr_timing is needed for this host? host->ddr_timing is the same.
Yes, but non-samsung hosts will not have have this property into their
dts file. So the code within the condition will not execute on
non-samsung hosts. SDR and DDR timing are required for Exynos5 SoC.
Yes, these are required only for Exynos Soc.
Non-samsung host will have default value here, but it seems to be meaningless.
Non-Samsung platforms will not have this property in their dts files.
This property is required on only those platforms that want to define
sdr and ddr timing values. It is not required on platforms that do no
use it.
quoted
quoted
quoted
+ else
+ host->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
+ if (of_property_read_u32_array(dev->of_node,
+ "samsung,dw-mshc-ddr-timing", timing, 3))
+ host->ddr_timing = DW_MCI_DEF_DDR_TIMING;
+ else
+ host->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
dev_info(dev, "fifo-depth property not found, using "
"value of FIFOTH register as default\n");
@@ -142,6 +144,17 @@/* Version ID register define */#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)+#define DW_MCI_DEF_SDR_TIMING 0x03030002+#define DW_MCI_DEF_DDR_TIMING 0x03020001
What is the basis for these timing?
These values is board-specific.
One missed comment?
Yes, sorry, missed this last time. These are default values for SDR
and DDR timing in case it is not specified in dts file. It may be
better to make it mandatory to specify the SDR and DDR property in dts
files (for Exynos5250) and remove this default values. Non-samsung
platforms or platforms not using this property are unaffected by this.
Is this patch considered only for exynos5250?
In case of exynos4210, the number of bits is different.
If upper macros is backward-compatible, it would be better.
These consider the Exynos4210 and Exynos4412 implementations as well.
The device tree documentation clearly states that the possible values
for each of the dividers. For Exynos4 SoC's, the divider value is
between 1 to 4 (or 0 to 3). So a bit mask of 7 is backward compatilble
for Exynos4.
Bit width is 2 for selclk_drv in exynos4210.
So bit mask of 3 is proper.
Let me clear it about divider value.
In case of Exynos4 SoC's, divider value(DIVRATIO) is reserved and host doesn't modify.
But value is fixed internally like following.
Exynos4210 : 2
Exynos4412 : 4
Ok. I will relook into this. Thanks.
Regards,
Thomas.
Kyungmin Park has already pointed .
It's not still proper place for board specific caps.
If I'm incorrect, please let me know.
And why MMC_CAP_CMD23 is default caps for all channel of hosts?
The cap listed above are specifying controller capabilities for dw-mmc
controllers on Exynos5 SoC. They are not board specific caps. All the
Exynos5 dw-mmc controllers can support MMC_CAP_CMD23 cap and hence, it
has been listed for all the controllers. Please let me know if you
feel there is any change required here.
MMC_CAP_8_BIT_DATA could be dependent on board.
A controller can have the MMC_CAP_8_BIT_DATA capability but the board
will decide the bus-width. The bus-width is specified in the dts files
of each board (or platform data). The bus-width for data transfer is
then decided by the MMC core code based on the caps and the bus-width
information. So MMC_CAP_8_BIT_DATA can be specified irrespective of
whether the board supports 8-bit or not.
quoted
I agree about MMC_CAP_CMD23.
Additionally, MMC_CAP_CMD23 is applied for dw-mmc host driver without regard to Exynos5.
The caps listed in exynos5250_dwmmc_caps is applicable only for
Exynos5 SoC's. Could you please let me know if there is anything
incorrect here.
I mean that MMC_CAP_CMD23 is a capability which is implemented in driver without dependency of SOC.
So, other soc also includes MMC_CAP_CMD23.
It'd rather make a default caps than list in specific soc, considering the other soc.
As you know, CLKSEL is specific for Samsung soc.
0x09C(CLKSEL) is reserved area in Synopsys memory map.
In case of non-samsung-soc, we cannot ensure this usage.
In previous version, I have suggested separating the variant into another file.
There is a check for type of SoC before using 0x9C as CLKSEL register.
Do you mean checking DW_MCI_TYPE_EXYNOS5250?
But Above two case(ddr_timing/sdr_timing), CLKSEL can be accessed on other soc's.
The tests have only been completed on Exynos5250. I do not have boards
for other Samsung SoC's which have a dw_mmc port connected and used on
the board. When we have other platforms tested with this patchset, we
can extend the 'if' check in the above code for other SoC's.
My meaning seem to be passed incorrectly.
+ if (ios->timing == MMC_TIMING_UHS_DDR50) {
regs |= (0x1 << slot->id) << 16;
- else
+ mci_writel(slot->host, CLKSEL, slot->host->ddr_timing);
What is the execution for non-samsung soc?
CLKSEL register is valid only for Exynos.
dw_mci_set_ios shoud be aware of this.
+ } else {
regs &= ~(0x1 << slot->id) << 16;
+ mci_writel(slot->host, CLKSEL, slot->host->sdr_timing);
This line is same.
+ }
+
quoted
quoted
Other implementations of dw-mmc might define custom register at 0x9C
Even so, register field can be different with Samsung soc.
Yes, with the correct checks for the type of SoC, differences in the
usage of 0x9C register can be handled.
quoted
quoted
but this will code will not execute on other SoC's and will not break
anything on other implementations. Regarding spliting this Exynos
specific code into another file, I prefer not to do it for now.
Spliting the code means adding new definitions of callback functions
which I am not sure is really required. The present code is fairly
simple one.
Yes, callback functions might be needed to accommodate various implementation
of host controller. It would be better to prepare this for other variant next.
Ok. I will relook at these patches and check if we really need split
these changes into a separate exynos specific file. If I again feel
that such a split is not required, I will reply back to you with
justification.
[...]
Host of non-samsung will reach here.
host->sdr_timing is needed for this host? host->ddr_timing is the same.
Yes, but non-samsung hosts will not have have this property into their
dts file. So the code within the condition will not execute on
non-samsung hosts. SDR and DDR timing are required for Exynos5 SoC.
Yes, these are required only for Exynos Soc.
Non-samsung host will have default value here, but it seems to be meaningless.
Non-Samsung platforms will not have this property in their dts files.
This property is required on only those platforms that want to define
sdr and ddr timing values. It is not required on platforms that do no
use it.
quoted
quoted
quoted
quoted
+ else
+ host->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
+ if (of_property_read_u32_array(dev->of_node,
+ "samsung,dw-mshc-ddr-timing", timing, 3))
+ host->ddr_timing = DW_MCI_DEF_DDR_TIMING;
+ else
+ host->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0],
+ timing[1], timing[2]);
+
if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
dev_info(dev, "fifo-depth property not found, using "
"value of FIFOTH register as default\n");
@@ -142,6 +144,17 @@/* Version ID register define */#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)+#define DW_MCI_DEF_SDR_TIMING 0x03030002+#define DW_MCI_DEF_DDR_TIMING 0x03020001
What is the basis for these timing?
These values is board-specific.
One missed comment?
Yes, sorry, missed this last time. These are default values for SDR
and DDR timing in case it is not specified in dts file. It may be
better to make it mandatory to specify the SDR and DDR property in dts
files (for Exynos5250) and remove this default values. Non-samsung
platforms or platforms not using this property are unaffected by this.
These value(0x03030002, 0x03020001) cannot be acceptable in specific board type of Exynos5250.
Assuming that timing values are not specified in dts file and board is different,
default values may be not proper. As you mentioned, other approach will be needed.
Thanks,
Seungwon Jeon
Is this patch considered only for exynos5250?
In case of exynos4210, the number of bits is different.
If upper macros is backward-compatible, it would be better.
These consider the Exynos4210 and Exynos4412 implementations as well.
The device tree documentation clearly states that the possible values
for each of the dividers. For Exynos4 SoC's, the divider value is
between 1 to 4 (or 0 to 3). So a bit mask of 7 is backward compatilble
for Exynos4.
Bit width is 2 for selclk_drv in exynos4210.
So bit mask of 3 is proper.
Let me clear it about divider value.
In case of Exynos4 SoC's, divider value(DIVRATIO) is reserved and host doesn't modify.
But value is fixed internally like following.
Exynos4210 : 2
Exynos4412 : 4
Ok. I will relook into this. Thanks.
Regards,
Thomas.
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