From: Will Deacon <hidden> Date: 2011-06-06 16:55:44
Hello,
Here is a patch series for adding support for the Cortex-A5 and
Cortex-A15 cores to Linux. The first two patches (from Pawel) are
already in Russell's patch system, but I included them here for
completeness.
Anyway, the main thing is the HWCAP stuff as the perf stuff is all
rather boring.
Enjoy!
Will
Pawel Moll (2):
arm: Convert v7 proc infos into a common macro
arm: Add Cortex A5 proc info
Will Deacon (9):
ARM: hwcaps: use shifts instead of hardcoded constants
ARM: hwcaps: add new HWCAP defines for ARMv7-A
ARM: proc: reorder macro parameters for __v7_proc macro
ARM: cortex-a5: add HWCAP_VFPv4D16 to proc info structure
ARM: proc: add proc info for Cortex-A15MP using classic page tables
ARM: perf: remove confusing comment from v7 perf events backend
ARM: perf: add PMUv2 common event definitions
ARM: perf: add support for the Cortex-A5 PMU
ARM: perf: add support for the Cortex-A15 PMU
arch/arm/include/asm/hwcap.h | 37 +++--
arch/arm/include/asm/perf_event.h | 2 +
arch/arm/kernel/perf_event.c | 6 +
arch/arm/kernel/perf_event_v7.c | 344 ++++++++++++++++++++++++++++++++++--
arch/arm/mm/proc-v7.S | 98 ++++++-----
5 files changed, 406 insertions(+), 81 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-06 16:55:45
From: Pawel Moll <redacted>
As most of the proc info content is common across all v7
processors, this patch converts existing A9 and generic v7
descriptions into a macro (allowing extra flags in future).
Signed-off-by: Pawel Moll <redacted>
---
arch/arm/mm/proc-v7.S | 67 +++++++++++++++++-------------------------------
1 files changed, 24 insertions(+), 43 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-06 16:55:47
The HWCAP numbers are defined as constants, each one being a power of 2.
This has become slightly unwieldy now that we have reached 32k.
This patch changes the HWCAP defines to use (1 << n) instead of coding
the constant directly. The values remain unchanged.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/include/asm/hwcap.h | 32 ++++++++++++++++----------------
1 files changed, 16 insertions(+), 16 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-06 16:55:48
Modern ARMv7-A cores can optionally implement these new hardware
features:
- VFPv4:
The latest version of the ARMv7 vector floating-point extensions,
including hardware support for fused multiple accumulate. D16 or D32
variants may be implemented.
- Integer divide:
The SDIV and UDIV instructions provide signed and unsigned integer
division in hardware. When implemented, these instructions may be
available in either both Thumb and ARM, or Thumb only.
This patch adds new HWCAP defines to describe these new features. The
integer divide capabilities are split into two bits for ARM and Thumb
respectively. Whilst HWCAP_IDIVA should never bet set if HWCAP_IDIVT is
clear, separating the bits makes it easier to interpret from userspace.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/include/asm/hwcap.h | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-06 16:55:49
The __v7_proc macro takes paramaters for mmu flags, io flags and hwcaps.
Since hwcaps tend to change more often between cores than the other
parameters, change the ordering so we don't have to provide empty values
for the flag arguments in the common case.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/mm/proc-v7.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-06 16:55:50
The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
processor.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/mm/proc-v7.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-06 16:55:51
Multicore implementations of the Cortex-A15 require bit 6 of the
auxiliary control register to be set in order for cache and TLB
maintenance operations to be broadcast between CPUs.
This patch adds a new proc_info structure for Cortex-A15, which enables
the SMP bit during setup and includes the new HWCAPs for integer
division and VFPv4.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/mm/proc-v7.S | 20 ++++++++++++++++++--
1 files changed, 18 insertions(+), 2 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-06 16:55:52
The comment about measuring TLB misses and refills in the ARMv7 perf
backend makes little sense and refers loosely to raw counters that
should be used instead.
This patch removes the comments to avoid any confusion.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/kernel/perf_event_v7.c | 10 ----------
1 files changed, 0 insertions(+), 10 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-06 16:55:53
The PMUv2 specification reserves a number of event encodings
for common events.
This patch adds these events to the common event enumeration
in preparation for PMUv2 cores, such as Cortex-A15.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/kernel/perf_event_v7.c | 35 +++++++++++++++++++++++++----------
1 files changed, 25 insertions(+), 10 deletions(-)
@@ -39,21 +45,30 @@ enum armv7_perf_types {*/ARMV7_PERFCTR_PC_WRITE=0x0C,ARMV7_PERFCTR_PC_IMM_BRANCH=0x0D,+ARMV7_PERFCTR_PC_PROC_RETURN=0x0E,ARMV7_PERFCTR_UNALIGNED_ACCESS=0x0F,++/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ARMV7_PERFCTR_PC_BRANCH_MIS_PRED=0x10,ARMV7_PERFCTR_CLOCK_CYCLES=0x11,--ARMV7_PERFCTR_PC_BRANCH_MIS_USED=0x12,+ARMV7_PERFCTR_PC_BRANCH_PRED=0x12,+ARMV7_PERFCTR_MEM_ACCESS=0x13,+ARMV7_PERFCTR_L1_ICACHE_ACCESS=0x14,+ARMV7_PERFCTR_L1_DCACHE_WB=0x15,+ARMV7_PERFCTR_L2_DCACHE_ACCESS=0x16,+ARMV7_PERFCTR_L2_DCACHE_REFILL=0x17,+ARMV7_PERFCTR_L2_DCACHE_WB=0x18,+ARMV7_PERFCTR_BUS_ACCESS=0x19,+ARMV7_PERFCTR_MEMORY_ERROR=0x1A,+ARMV7_PERFCTR_INSTR_SPEC=0x1B,+ARMV7_PERFCTR_TTBR_WRITE=0x1C,+ARMV7_PERFCTR_BUS_CYCLES=0x1D,ARMV7_PERFCTR_CPU_CYCLES=0xFF};/* ARMv7 Cortex-A8 specific event types */enumarmv7_a8_perf_types{-ARMV7_PERFCTR_INSTR_EXECUTED=0x08,--ARMV7_PERFCTR_PC_PROC_RETURN=0x0E,-ARMV7_PERFCTR_WRITE_BUFFER_FULL=0x40,ARMV7_PERFCTR_L2_STORE_MERGED=0x41,ARMV7_PERFCTR_L2_STORE_BUFF=0x42,
From: Jean Pihet <hidden> Date: 2011-06-07 07:18:50
Hi Will,
On Mon, Jun 6, 2011 at 6:55 PM, Will Deacon [off-list ref] wrote:
quoted hunk
The PMUv2 specification reserves a number of event encodings
for common events.
This patch adds these events to the common event enumeration
in preparation for PMUv2 cores, such as Cortex-A15.
Signed-off-by: Will Deacon <redacted>
---
?arch/arm/kernel/perf_event_v7.c | ? 35 +++++++++++++++++++++++++----------
?1 files changed, 25 insertions(+), 10 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-07 08:51:27
Hi Jean,
Thanks for looking at this bag of hex values!
On Mon, Jun 6, 2011 at 6:55 PM, Will Deacon [off-list ref] wrote:
quoted
The PMUv2 specification reserves a number of event encodings
for common events.
This patch adds these events to the common event enumeration
in preparation for PMUv2 cores, such as Cortex-A15.
Signed-off-by: Will Deacon <redacted>
---
?arch/arm/kernel/perf_event_v7.c | ? 35 +++++++++++++++++++++++++----------
?1 files changed, 25 insertions(+), 10 deletions(-)
Will ARMV7_PERFCTR_INSTR_EXECUTED and ARMV7_PERFCTR_PC_PROC_RETURN
work for all v7 implementations? For example they are not defined for
A9.
Correct, A9 doesn't support these and in general they are not mandatory.
The useful part is that this event space cannot be reused for different
events, so if an event of encoding 0x08 *is* supported, it absolutely
must be ARMV7_PERFCTR_INSTR_EXECUTED.
PMUv2 does define some feature registers (bitmaps) in the co-processor
space, which tell you the supported events out of the common encodings.
I don't think this is much use for the kernel, but it might be for
userspace. If somebody decides they want it then I'll happily expose it
through debugfs.
From: Dave Martin <hidden> Date: 2011-06-07 16:17:36
On Mon, Jun 06, 2011 at 05:55:50PM +0100, Will Deacon wrote:
quoted hunk
The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
processor.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/mm/proc-v7.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
From: Dave Martin <hidden> Date: 2011-06-07 16:18:27
On Mon, Jun 06, 2011 at 05:55:51PM +0100, Will Deacon wrote:
quoted hunk
Multicore implementations of the Cortex-A15 require bit 6 of the
auxiliary control register to be set in order for cache and TLB
maintenance operations to be broadcast between CPUs.
This patch adds a new proc_info structure for Cortex-A15, which enables
the SMP bit during setup and includes the new HWCAPs for integer
division and VFPv4.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/mm/proc-v7.S | 20 ++++++++++++++++++--
1 files changed, 18 insertions(+), 2 deletions(-)
From: Will Deacon <hidden> Date: 2011-06-07 16:22:04
On Tue, Jun 07, 2011 at 05:17:36PM +0100, Dave Martin wrote:
On Mon, Jun 06, 2011 at 05:55:50PM +0100, Will Deacon wrote:
quoted
The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
processor.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/mm/proc-v7.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Is VFPv4 a superset of VFPv3? If so, should we also include
HWCAP_VFPv3D16 (and what about HWCAP_VFP)?
Actually, it looks like this shouldn't be declared statically at all, since the
kernel have not have VFP support compiled in. Rather, the vfp code will detect
the capability and adjust elf_hwcap at runtime.
Will
From: Dave Martin <hidden> Date: 2011-06-08 09:05:01
On Tue, Jun 07, 2011 at 05:22:04PM +0100, Will Deacon wrote:
On Tue, Jun 07, 2011 at 05:17:36PM +0100, Dave Martin wrote:
quoted
On Mon, Jun 06, 2011 at 05:55:50PM +0100, Will Deacon wrote:
quoted
The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
processor.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/mm/proc-v7.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Is VFPv4 a superset of VFPv3? If so, should we also include
HWCAP_VFPv3D16 (and what about HWCAP_VFP)?
Actually, it looks like this shouldn't be declared statically at all, since the
kernel have not have VFP support compiled in. Rather, the vfp code will detect
the capability and adjust elf_hwcap at runtime.
From: Will Deacon <hidden> Date: 2011-06-08 09:24:39
On Wed, Jun 08, 2011 at 10:05:01AM +0100, Dave Martin wrote:
On Tue, Jun 07, 2011 at 05:22:04PM +0100, Will Deacon wrote:
quoted
On Tue, Jun 07, 2011 at 05:17:36PM +0100, Dave Martin wrote:
quoted
On Mon, Jun 06, 2011 at 05:55:50PM +0100, Will Deacon wrote:
quoted
The Cortex-A5 implements VFPv4D16, so add this to the hwcaps for this
processor.
Signed-off-by: Will Deacon <redacted>
---
arch/arm/mm/proc-v7.S | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Is VFPv4 a superset of VFPv3? If so, should we also include
HWCAP_VFPv3D16 (and what about HWCAP_VFP)?
Actually, it looks like this shouldn't be declared statically at all, since the
kernel have not have VFP support compiled in. Rather, the vfp code will detect
the capability and adjust elf_hwcap at runtime.
Hah, yes, quite right. My bad.
I'll fix it for v2.
As for the D16 stuff, I've had a better idea [need to check with the tools
guys]. Rather than waste two bits for VFPv4 and VFPv4D16, it should probably
be something like:
VFPv3 : HWCAP_VFPv3
VFPv3D16 : HWCAP_VFPv3 | HWCAP_VFPv3D16
VFPv4 : HWCAP_VFPv3 | HWCAP_VFPv4
VFPv4D16 : HWCAP_VFPv3 | HWCAP_VFPv3D16 | HWCAP_VFPv4
Will