From: hashim alig <hidden> Date: 2010-09-28 13:25:11
Hi,
I am using linux-2.6.32 kernel on a platform which is ARM-Cortex A9
SMP (dual core, each at 500 MHz) with PL310 as the L2 cache. I observe
high latency in cache maintainance operations (both invalidation and
clean) which is around 90 cycles for every cache line (32 bytes).
Is it normal? What should be the practical range ?
I also tried with linux-2.6.35 over which I applied few L2 patches
from Catalin but observation remains same.
regards
Hashim
On Tue, 2010-09-28 at 14:25 +0100, hashim alig wrote:
I am using linux-2.6.32 kernel on a platform which is ARM-Cortex A9
SMP (dual core, each at 500 MHz) with PL310 as the L2 cache. I observe
high latency in cache maintainance operations (both invalidation and
clean) which is around 90 cycles for every cache line (32 bytes).
Is it normal? What should be the practical range ?
I also tried with linux-2.6.35 over which I applied few L2 patches
from Catalin but observation remains same.
On Tue, 2010-09-28 at 15:49 +0100, Catalin Marinas wrote:
On Tue, 2010-09-28 at 14:25 +0100, hashim alig wrote:
quoted
I am using linux-2.6.32 kernel on a platform which is ARM-Cortex A9
SMP (dual core, each at 500 MHz) with PL310 as the L2 cache. I observe
high latency in cache maintainance operations (both invalidation and
clean) which is around 90 cycles for every cache line (32 bytes).
Is it normal? What should be the practical range ?
I also tried with linux-2.6.35 over which I applied few L2 patches
from Catalin but observation remains same.
Forgot to mention - this patch is for Versatile Express, you would need
to do something similar in your platform. We can't really set the
default values in the l2x0 code since these latencies depend on the
hardware configuration.
--
Catalin
From: hashim alig <hidden> Date: 2010-09-29 06:06:52
Hello Catalin,
On Tue, Sep 28, 2010 at 8:20 PM, Catalin Marinas
[off-list ref] wrote:
On Tue, 2010-09-28 at 15:49 +0100, Catalin Marinas wrote:
quoted
On Tue, 2010-09-28 at 14:25 +0100, hashim alig wrote:
quoted
I am using linux-2.6.32 kernel on a platform which is ARM-Cortex A9
SMP (dual core, each at 500 MHz) with PL310 as the L2 cache. I observe
high latency in cache maintainance operations (both invalidation and
clean) which is around 90 cycles for every cache line (32 bytes).
Is it normal? What should be the practical range ?
I also tried with linux-2.6.35 over which I applied few L2 patches
from Catalin but observation remains same.
Forgot to mention - this patch is for Versatile Express, you would need
to do something similar in your platform. We can't really set the
default values in the l2x0 code since these latencies depend on the
hardware configuration.
OK. I have actually played with latency registers but saw no
improvement, even the system
became unstable.
Following is the ideal configuration of PL310 registers (as reported
by h/w designers) and on which L2 and system is stable.
Auxillary Control Reg (0x104) - 0x02060000
Tag RAM Latency (0x108) - 0x00000110
Data RAM Latency (0x10C) - 0x00000220
One more thing, port filtering at L2 is enabled with following configuration
Addr filtering start (offset 0xc00) - 0x1
Addr filtering end (offset 0xc04) - 0x08000000
regards
Shiraz
On Wed, 2010-09-29 at 07:06 +0100, hashim alig wrote:
On Tue, Sep 28, 2010 at 8:20 PM, Catalin Marinas
[off-list ref] wrote:
quoted
On Tue, 2010-09-28 at 15:49 +0100, Catalin Marinas wrote:
quoted
On Tue, 2010-09-28 at 14:25 +0100, hashim alig wrote:
quoted
I am using linux-2.6.32 kernel on a platform which is ARM-Cortex A9
SMP (dual core, each at 500 MHz) with PL310 as the L2 cache. I observe
high latency in cache maintainance operations (both invalidation and
clean) which is around 90 cycles for every cache line (32 bytes).
Is it normal? What should be the practical range ?
I also tried with linux-2.6.35 over which I applied few L2 patches
from Catalin but observation remains same.
There are a couple of commits that made a difference in the L2
maintenance - 0eb948dd7f7 and 3d1074349b (reducing the amount of
spinlock operations, merged in 2.6.33). Do you have these applied?
--
Catalin
From: hashim alig <hidden> Date: 2010-10-01 11:46:16
Hello Catalin,
On Wed, Sep 29, 2010 at 2:25 PM, Catalin Marinas
[off-list ref] wrote:
On Wed, 2010-09-29 at 07:06 +0100, hashim alig wrote:
quoted
On Tue, Sep 28, 2010 at 8:20 PM, Catalin Marinas
[off-list ref] wrote:
quoted
On Tue, 2010-09-28 at 15:49 +0100, Catalin Marinas wrote:
quoted
On Tue, 2010-09-28 at 14:25 +0100, hashim alig wrote:
quoted
I am using linux-2.6.32 kernel on a platform which is ARM-Cortex A9
SMP (dual core, each at 500 MHz) with PL310 as the L2 cache. I observe
high latency in cache maintainance operations (both invalidation and
clean) which is around 90 cycles for every cache line (32 bytes).
Is it normal? What should be the practical range ?
I also tried with linux-2.6.35 over which I applied few L2 patches
from Catalin but observation remains same.
There are a couple of commits that made a difference in the L2
maintenance - 0eb948dd7f7 and 3d1074349b (reducing the amount of
spinlock operations, merged in 2.6.33). Do you have these applied?
I tried them along with
0a5f4cb2fc14026c3883aae6d6f6d5aaf9a0ae4a
ARM: Improve the L2 cache performance when PL310 is used
but still I am getting high latencies. To clean and invalidate 2048
bytes its is taking 11-12 usecs.
Surprisingly clean and invalidate(only) operations are taking similar time.
I though that invalidation should take less cycles.
regards
Hashim