--- v24
+++ v23
@@ -6,63 +6,17 @@
IBT state machine is described in Intel SDM Vol. 1, Sec. 18.3.
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
-Cc: Kees Cook <keescook@chromium.org>
+Reviewed-by: Kees Cook <keescook@chromium.org>
---
-v24:
-- Update for changes from splitting shadow stack and ibt.
+ arch/x86/kernel/cet.c | 26 ++++++++++++++++++++++++--
+ arch/x86/kernel/fpu/signal.c | 8 +++++---
+ 2 files changed, 29 insertions(+), 5 deletions(-)
- arch/x86/kernel/fpu/signal.c | 30 +++++++++++++++++++++++++++---
- 1 file changed, 27 insertions(+), 3 deletions(-)
-
-diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
-index 2e56f2fe8be0..1f54c18607c9 100644
---- a/arch/x86/kernel/fpu/signal.c
-+++ b/arch/x86/kernel/fpu/signal.c
-@@ -71,16 +71,32 @@ int save_extra_state_to_sigframe(int ia32, void __user *fp, unsigned long restor
- return err;
-
- ext.ssp = token_addr;
-+ }
-
-+ if (new_ssp || cet->ibt_enabled) {
- fpregs_lock();
- if (test_thread_flag(TIF_NEED_FPU_LOAD))
- __fpregs_load_activate();
-+
- if (new_ssp)
- wrmsrl(MSR_IA32_PL3_SSP, new_ssp);
-+
-+ if (cet->ibt_enabled) {
-+ u64 r;
-+
-+ rdmsrl(MSR_IA32_U_CET, r);
-+
-+ if (r & CET_WAIT_ENDBR) {
-+ ext.wait_endbr = 1;
-+ r &= ~CET_WAIT_ENDBR;
-+ wrmsrl(MSR_IA32_U_CET, r);
-+ }
-+ }
-+
- fpregs_unlock();
- }
-
-- if (ext.ssp) {
-+ if (ext.ssp || cet->ibt_enabled) {
- void __user *p = fp;
-
- ext.total_size = sizeof(ext);
-@@ -110,7 +126,8 @@ static int get_extra_state_from_sigframe(int ia32, void __user *fp, struct sc_ex
- if (!cpu_feature_enabled(X86_FEATURE_CET))
- return 0;
-
-- if (!cet->shstk_size)
-+ if (!cet->shstk_size &&
-+ !cet->ibt_enabled)
- return 0;
-
- memset(ext, 0, sizeof(*ext));
-@@ -162,6 +179,13 @@ void restore_extra_state(struct sc_ext *sc_ext)
+diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c
+index 3361706ba950..34a26eb7f259 100644
+--- a/arch/x86/kernel/cet.c
++++ b/arch/x86/kernel/cet.c
+@@ -300,6 +300,13 @@ void cet_restore_signal(struct sc_ext *sc_ext)
msr_val |= CET_SHSTK_EN;
}
@@ -76,14 +30,65 @@
if (test_thread_flag(TIF_NEED_FPU_LOAD))
cet_user_state->user_cet = msr_val;
else
-@@ -626,7 +650,7 @@ static unsigned long fpu__alloc_sigcontext_ext(unsigned long sp)
+@@ -340,9 +347,24 @@ int cet_setup_signal(bool ia32, unsigned long rstor_addr, struct sc_ext *sc_ext)
+ sc_ext->ssp = new_ssp;
+ }
+
+- if (ssp) {
++ if (ssp || cet->ibt_enabled) {
+ start_update_msrs();
+- wrmsrl(MSR_IA32_PL3_SSP, ssp);
++
++ if (ssp)
++ wrmsrl(MSR_IA32_PL3_SSP, ssp);
++
++ if (cet->ibt_enabled) {
++ u64 r;
++
++ rdmsrl(MSR_IA32_U_CET, r);
++
++ if (r & CET_WAIT_ENDBR) {
++ sc_ext->wait_endbr = 1;
++ r &= ~CET_WAIT_ENDBR;
++ wrmsrl(MSR_IA32_U_CET, r);
++ }
++ }
++
+ end_update_msrs();
+ }
+
+diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
+index 270e4649f435..b914d74c8ba6 100644
+--- a/arch/x86/kernel/fpu/signal.c
++++ b/arch/x86/kernel/fpu/signal.c
+@@ -57,7 +57,8 @@ int save_cet_to_sigframe(int ia32, void __user *fp, unsigned long restorer)
+ {
+ int err = 0;
+
+- if (!current->thread.cet.shstk_size)
++ if (!current->thread.cet.shstk_size &&
++ !current->thread.cet.ibt_enabled)
+ return 0;
+
+ if (fp) {
+@@ -89,7 +90,8 @@ static int get_cet_from_sigframe(int ia32, void __user *fp, struct sc_ext *ext)
+
+ memset(ext, 0, sizeof(*ext));
+
+- if (!current->thread.cet.shstk_size)
++ if (!current->thread.cet.shstk_size &&
++ !current->thread.cet.ibt_enabled)
+ return 0;
+
+ if (fp) {
+@@ -577,7 +579,7 @@ static unsigned long fpu__alloc_sigcontext_ext(unsigned long sp)
* sigcontext_ext is at: fpu + fpu_user_xstate_size +
* FP_XSTATE_MAGIC2_SIZE, then aligned to 8.
*/
- if (cet->shstk_size)
+ if (cet->shstk_size || cet->ibt_enabled)
sp -= (sizeof(struct sc_ext) + 8);
- #endif
+
return sp;
--
2.21.0