On Sat, Sep 13, 2014 at 05:34:11PM +0300, Kevin Wilson wrote:

Hi,
I have a single source file which I wrote, implementing a kernel
module: helloworld.c

In order to built it, I prepared the following Makefile:

obj-m += helloworld.o

all:
     make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules

clean:
     make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean



Is it ok ? or should the obj-m parameter be *different* than the the
source file (without the *.o suffix)
(something like obj-m += hello.o ?)

Does the above work for you?

Have you read the kernel documentation about how to write stand-alone
Makefiles?  It should answer this question for you, right?

thanks,

greg k-h