@@ -64,6 +64,7 @@ static void store_all(int i915)
 		.buffer_count = 2,
 	};
 	const struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
 	int reloc_sz = sizeof(uint32_t);
 	unsigned int nengine, value;
 	void *cs;

@@ -88,7 +89,9 @@ static void store_all(int i915)
 
 	nengine = 0;
 	cs = gem_mmap__device_coherent(i915, obj[1].handle, 0, sz, PROT_WRITE);
-	__for_each_physical_engine(i915, e) {
+
+	ctx = intel_ctx_create_all_physical(i915);
+	for_each_ctx_engine(i915, ctx, e) {
 		uint64_t addr;
 
 		igt_assert(reloc.presumed_offset != -1);

@@ -103,6 +106,7 @@ static void store_all(int i915)
 		if (gen < 6)
 			execbuf.flags |= I915_EXEC_SECURE;
 		execbuf.flags |= I915_EXEC_NO_RELOC | I915_EXEC_HANDLE_LUT;
+		execbuf.rsvd1 = ctx->id;
 
 		memcpy(cs + execbuf.batch_start_offset, batch, sizeof(batch));
 		memcpy(cs + reloc.offset, &addr, reloc_sz);

@@ -121,6 +125,7 @@ static void store_all(int i915)
 	memset(engines, 0xdeadbeef, sizeof(engines));
 	gem_read(i915, obj[0].handle, 0, engines, nengine * sizeof(engines[0]));
 	gem_close(i915, obj[0].handle);
+	intel_ctx_destroy(i915, ctx);
 
 	for (i = 0; i < nengine; i++)
 		igt_assert_eq_u32(engines[i], i);