[dpdk-dev] why uses the cldemote here in dpdk21.02?

vic_yf · 2021-05-19T14:09:26+0800

Hi, when I read the dpdk dlb eventdev driver code, I find that it used the cldemote instruction in the dlb_recv_qe(). But I don't understand why it used there? The cldemote instruction means to move the cache line to the more remote cache, which helps to accelerate core-to-core communication. But who will be use the memory of cache_line_base? >static __rte_always_inline int dlb_recv_qe(struct dlb_port *qm_port, struct dlb_dequeue_qe *qe, uint8_t *offset) >{ > > cq_addr = dlb_port[qm_port->id][PORT_TYPE(qm_port)].cq_base; > cq_addr = &cq_addr[qm_port->cq_idx]; > cache_line_base = (void *)(((uintptr_t)cq_addr) & ~0x3F); > *offset = ((uintptr_t)cq_addr & 0x30) >> 4; > /* Load the next CQ cache line from memory. Pack these reads as tight > * as possible to reduce the chance that DLB invalidates the line while > * the CPU is reading it. Read the cache line backwards to ensure that > * if QE[N] (N > 0) is valid, then QEs[0:N-1] are too. > * > * (Valid QEs start at &qe[offset]) > */ > qes[3] = _mm_load_si128((__m128i *)&cache_line_base[6]); > qes[2] = _mm_load_si128((__m128i *)&cache_line_base[4]); > qes[1] = _mm_load_si128((__m128i *)&cache_line_base[2]);...

From: vic_yf <hidden>
Date: 2021-05-20 08:01:15

Hi,
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; when I read the&nbsp; dpdk dlb eventdev driver code, I find that it&nbsp; used the cldemote instruction in the dlb_recv_qe(). But I don't understand why it used there?&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; The cldemote instruction means to move the cache line to the more remote cache, which helps to  accelerate core-to-core communication. But who will be use the memory of  cache_line_base?



&gt;static __rte_always_inline int dlb_recv_qe(struct dlb_port *qm_port, struct dlb_dequeue_qe *qe, 	    uint8_t *offset) 

&gt;{
&gt; 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cq_addr = dlb_port[qm_port-&gt;id][PORT_TYPE(qm_port)].cq_base; 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cq_addr = &amp;cq_addr[qm_port-&gt;cq_idx]; 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; cache_line_base = (void *)(((uintptr_t)cq_addr) &amp; ~0x3F); 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *offset = ((uintptr_t)cq_addr &amp; 0x30) &gt;&gt; 4; 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Load the next CQ cache line from memory. Pack these reads as tight 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * as possible to reduce the chance that DLB invalidates the line while 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * the CPU is reading it. Read the cache line backwards to ensure that 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * if QE[N] (N &gt; 0) is valid, then QEs[0:N-1] are too. 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; *
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; * (Valid QEs start at &amp;qe[offset]) 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; */ 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; qes[3] = _mm_load_si128((__m128i *)&amp;cache_line_base[6]);
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; qes[2] = _mm_load_si128((__m128i *)&amp;cache_line_base[4]); 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; qes[1] = _mm_load_si128((__m128i *)&amp;cache_line_base[2]); 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; qes[0] = _mm_load_si128((__m128i *)&amp;cache_line_base[0]); 

&gt;
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /* Evict the cache line ASAP */ 

&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; rte_cldemote(cache_line_base);


Thanks.

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