Reviews by anup@brainfault.org · cip-dev

All review-attestation trailers (Reviewed-by / Acked-by / Tested-by / Reported-by / Suggested-by / Co-developed-by / Reported-and-tested-by) by this address on the cip-dev archive.

11 attestations . (11 Reviewed-by)

• STALE889d REVIEWED: 13 (10M) [PATCH v2 5.10.y-cip 21/44] clocksource/drivers/riscv: Increase the clock source rating
  2024-02-06 · Reviewed-by
• STALE889d REVIEWED: 6 (5M) [PATCH v2 5.10.y-cip 15/44] irqchip/sifive-plic: Improve naming scheme for per context offsets
  2024-02-06 · Reviewed-by
• STALE889d REVIEWED: 6 (5M) [PATCH v2 5.10.y-cip 16/44] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode
  2024-02-06 · Reviewed-by
• STALE890d REVIEWED: 12 (10M) [PATCH 5.10.y-cip 25/48] clocksource/drivers/riscv: Increase the clock source rating
  2024-02-05 · Reviewed-by
• STALE890d REVIEWED: 5 (5M) [PATCH 5.10.y-cip 19/48] irqchip/sifive-plic: Improve naming scheme for per context offsets
  2024-02-05 · Reviewed-by
• STALE890d REVIEWED: 5 (5M) [PATCH 5.10.y-cip 20/48] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode
  2024-02-05 · Reviewed-by
• STALE891d REVIEWED: 12 (10M) [RFC PATCH 5.10.y-cip 16/39] clocksource/drivers/riscv: Increase the clock source rating
  2024-01-30 · Reviewed-by
• STALE891d REVIEWED: 5 (5M) [RFC PATCH 5.10.y-cip 10/39] irqchip/sifive-plic: Improve naming scheme for per context offsets
  2024-01-30 · Reviewed-by
• STALE891d REVIEWED: 5 (5M) [RFC PATCH 5.10.y-cip 11/39] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode
  2024-01-30 · Reviewed-by
• STALE915d REVIEWED: 12 (10M) [PATCH 6.1.y-cip 04/30] clocksource/drivers/riscv: Increase the clock source rating
  2024-01-08 · Reviewed-by
• STALE924d REVIEWED: 12 (10M) [PATCH RFC 04/30] clocksource/drivers/riscv: Increase the clock source rating
  2023-12-20 · Reviewed-by