@@ -7,6 +7,10 @@ config ARCH_TEXT_BASE
 	default 0x68000000 if ARCH_RK3188
 	default 0x0 if ARCH_RK3288
 
+config RK_TIMER
+	hex
+	default 1
+
 choice
 	prompt "Select Rockchip SoC"
 

@@ -15,6 +19,7 @@ config ARCH_RK3188
 
 config ARCH_RK3288
 	bool "Rockchip RK3288 SoCs"
+	select CLOCKSOURCE_ROCKCHIP
 endchoice
 
 comment "select Rockchip boards:"

@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_TIMER_H
+#define _ASM_ARCH_TIMER_H
+
+struct rk_timer {
+	unsigned int timer_load_count0;
+	unsigned int timer_load_count1;
+	unsigned int timer_curr_value0;
+	unsigned int timer_curr_value1;
+	unsigned int timer_ctrl_reg;
+	unsigned int timer_int_status;
+};
+
+#endif

@@ -49,3 +49,7 @@ config CLOCKSOURCE_ORION
 config CLOCKSOURCE_UEMD
 	bool
 	depends on ARCH_UEMD
+
+config CLOCKSOURCE_ROCKCHIP
+	bool
+	depends on ARCH_ROCKCHIP

@@ -7,3 +7,4 @@ obj-$(CONFIG_CLOCKSOURCE_MVEBU)   += mvebu.o
 obj-$(CONFIG_CLOCKSOURCE_NOMADIK) += nomadik.o
 obj-$(CONFIG_CLOCKSOURCE_ORION)   += orion.o
 obj-$(CONFIG_CLOCKSOURCE_UEMD)    += uemd.o
+obj-$(CONFIG_CLOCKSOURCE_ROCKCHIP)+= rk_timer.o

@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * (C) Copyright 2016 PHYTEC Messtechnik GmbH
+ * Author: Wadim Egorov <w.egorov@phytec.de>
+
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <clock.h>
+#include <init.h>
+#include <io.h>
+#include <mach/timer.h>
+#include <stdio.h>
+#include <mach/hardware.h>
+#include <mach/cru_rk3288.h>
+#include <common.h>
+
+struct rk_timer *timer_ptr;
+
+static uint64_t rockchip_get_ticks(void)
+{
+	uint64_t timebase_h, timebase_l;
+
+	timebase_l = readl(&timer_ptr->timer_curr_value0);
+	timebase_h = readl(&timer_ptr->timer_curr_value1);
+
+	return timebase_h << 32 | timebase_l;
+}
+
+static struct clocksource rkcs = {
+	.read   = rockchip_get_ticks,
+	.mask   = CLOCKSOURCE_MASK(32),
+	.shift  = 10,
+};
+
+static int rockchip_timer_probe(struct device_d *dev)
+{
+	struct resource *iores;
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+	timer_ptr = IOMEM(iores->start) + 0x20 * CONFIG_RK_TIMER;
+
+	rkcs.mult = clocksource_hz2mult(OSC_HZ, rkcs.shift);
+
+	writel(0xffffffff, &timer_ptr->timer_load_count0);
+	writel(0xffffffff, &timer_ptr->timer_load_count1);
+	writel(1, &timer_ptr->timer_ctrl_reg);
+
+	return init_clock(&rkcs);
+}
+
+static __maybe_unused struct of_device_id rktimer_dt_ids[] = {
+	{
+		.compatible = "rockchip,rk3288-timer",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct driver_d rktimer_driver = {
+	.name = "rockchip-timer",
+	.probe = rockchip_timer_probe,
+	.of_compatible = DRV_OF_COMPAT(rktimer_dt_ids),
+};
+
+static int rktimer_init(void)
+{
+	return platform_driver_register(&rktimer_driver);
+}
+core_initcall(rktimer_init);